A methodology to evaluate memory architecture design tradeoffs for video signal processors

Dutta, Santanu; Wolf, Wayne; Wolfe, Andrew

doi:10.1109/76.660828

Cited by 26 publications

(10 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Memory system design for video processors [9] had constraints on area, cycle time. [10] proposed data memory size and number of cycles as design metrics.…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach for Estimation and Optimization of Memory In Low Power Embedded Systems

Srilatha¹,

Rao²

2009

IJCTE

View full text Add to dashboard Cite

-The paper describes a method for estimation and optimization of memory size in low power embedded systems. This approach can be treated as a pathfinder to efficiently optimize the memory module, in turn optimizing the design time. It can be even employed for high level memory exploration applications while successfully meeting the performance -cost design metrics of the system. The paper concludes with an implementation example of a Speech Recognition module, showing an effective reduction in the memory requirement of the system after memory optimization. Depending upon the results, even algorithm based optimization can be done with an aim of further reducing the memory size.

show abstract

“…Memory system design for video processors [9] had constraints on area, cycle time. [10] proposed data memory size and number of cycles as design metrics.…”

Section: Related Workmentioning

confidence: 99%

A Novel Approach for Estimation and Optimization of Memory In Low Power Embedded Systems

Srilatha¹,

Rao²

2009

IJCTE

View full text Add to dashboard Cite

show abstract

“…Moreover, we also optimize the on-chip power consumption where SRAM power is related to the memory size in Eq. (2).…”

Section: Data Localitymentioning

confidence: 99%

“…Compared to prevalent MPEG-x and H.26x video standards, H.264/AVC [1] decodes present pixel from a long history of pixel data and therefore requires much intermediate storage for VLSI implementation. Therefore, this high data correlation or dependency leads to a great challenge of memory subsystem in designing multimedia systems [2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

Liu¹,

Lee²

2007

J Sign Process Syst Sign Image

View full text Add to dashboard Cite

Abstract. This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocating memory space but inducing large silicon area and power consumption as well. We first review the existing solutions and propose a three-level memory hierarchy with line-pixel-lookahead to improve access efficiency. Three-level memory hierarchy includes registers, content/slice SRAM and external frame DRAM. We emphasize the need to consider the secondary hierarchy, content/slice SRAM, during the design of an H.264/AVC decoder. Specifically, we introduce a slice SRAM and line-pixel-lookahead to lower the memory capacity and external bandwidth. This SRAM stores neighboring pixels and prevents the data re-access from DRAM. Linepixel-lookahead exploits multi-dimensional pixel locality so as to averagely improve prediction performance by 6.54% compared to conventional vertical prediction. Simulation results also reveal that the proposal makes a better trade-off between memory allocation and external bandwidth as well as power, leading to 50% of memory power reduction compared to the design without exploiting the secondary slice SRAM hierarchy.

show abstract

“…Double buffering increases memory size but is essential for pipelined parallel processing. Design issues associated with memory architectures of multimedia processing have been studied in more detail in [24,25].…”

Section: Shared Vs Local Data Memory Approachmentioning

confidence: 99%

Scalable Architecture for SoC Video Encoders

Kangas

Hämäläinen

Kuusilinna

2006

J VLSI Sign Process Syst Sign Image Video Technol

View full text Add to dashboard Cite

Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

show abstract

A methodology to evaluate memory architecture design tradeoffs for video signal processors

Cited by 26 publications

References 13 publications

A Novel Approach for Estimation and Optimization of Memory In Low Power Embedded Systems

A Novel Approach for Estimation and Optimization of Memory In Low Power Embedded Systems

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead

Scalable Architecture for SoC Video Encoders

Contact Info

Product

Resources

About