A timing model for static CMOS gates

Chen, H.-Y.; Dutta, Santanu

doi:10.1109/iccad.1989.76907

Cited by 25 publications

(9 citation statements)

References 6 publications

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“…The equivalent-inverter equations and the method followed to derive them are different from the ones we :proposed in an earlier paper [12]. We will not go into the details of the derivation, but will mention the results and point out the differences.…”

Section: Equivalent Inverter Mappingmentioning

confidence: 91%

“…We will not go into the details of the derivation, but will mention the results and point out the differences. Following the differences given here and the steps mentioned in [12], the derivation of the resulting formulae is straightforward. The formulae given below apply to a NAND gate; the NOR-gate equivalent can be derived by iinterchanging the subscripts ( n and p) and the transition cases (input-rising and input-falling) for the NAND.…”

Section: Equivalent Inverter Mappingmentioning

confidence: 99%

“…whether the input to the gate is rising or falling), and some technology-dependent parameters th,at determine the junction capacitances associated with the transistor terminals. The inverter mapping, details of which are given in [12], consists of two parts -finding the equivalent-inverter width and calculating the modeling-capacitance a t the inverter output.…”

Section: Equivalent Inverter Mappingmentioning

confidence: 99%

“…This model has been found to be in reasonable agreement with SPICE for typical circuit sizes and loading. For static gates other than the inverter, we use a scheme very similar t o the one in [12], by which each gate is mapped to an equivalent inverter having an equivalent output capacitance. The size of the inverter and the value of the modeling capacitor depend upon the gate-type, the gate size, the switching input, the input transition, and the process technology.…”

Section: Introductionmentioning

confidence: 99%

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ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

Dutta

Nag

Roy

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

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This paper introduces an automated transistor sizing tool (ASAP) that incorporates accurate gatelevel functio~nal models and can be used for delay, area, and power optimization of CMOS combinational logic circuits in a VLSI design environment. ASAP considers the performailce improvement of VLSI CMOS circuits by optimally sizing the transistors on the first N critical paths. The global picture of the circuit is considered by taking into account the effects that the transi.stor size changes of one path have on the others. The optimization technique in our sizing tool is based on simulated annealing and couples accurate delay modeling with power and area optimization. The combinatorial minimization of the objective function relies on analytical models that can accurately evaluate the delay, the power and the area of a gate. ASAP has been implemented in C on an Apollo 400 workstation with encouraging results.

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Section: Equivalent Inverter Mappingmentioning

confidence: 91%

Section: Equivalent Inverter Mappingmentioning

confidence: 99%

Section: Equivalent Inverter Mappingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

ASAP: a transistor sizing tool for speed, area, and power optimization of static CMOS circuits

Dutta

Nag

Roy

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94

Self Cite

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show abstract

“…However, while the case of single-input switching has received a lot of attention, the proximity effect is just starting to be addressed in the literature. Many attempts to model the delay of multiinput gates assume only one input is switching [3], [11], [15] and thus do not take temporal proximity of input transitions into account. We now review the research that does consider multiple switching inputs.…”

Section: Introductionmentioning

confidence: 99%