A comprehensive delay model for CMOS inverters

Dutta, Santanu; Shetti, S. S. Mahant; Lusky, S.

doi:10.1109/4.400428

Cited by 93 publications

(30 citation statements)

References 7 publications

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“…However, this neglect is not valid in the latter case when the input is very slow compared to the output. Linearity between T inp and T out has been demonstrated in [7] from the simulations of an inverter. For all input transition times greater than a certain critical value (T inp0 ), a linear relationship between T inp and T out exists:…”

Section: Mostly Input Dependentmentioning

confidence: 95%

Scalable Gate-Level Models for Power and Timing Analysis

Badaroglu

Plas

Wambacq

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this paper we present a macromodeling methodology to accurately reproduce the timing and the peak/average power behaviors of digital standard cells for a wide range of operating conditions determined by the load, the input transition time, and the supply variations. Our methodology significantly reduces the number of transient simulations for the cell characterization. The numerical results for the transient simulation of large digital systems indicate that we achieve a mean error of 10% for the power consumption and 4% for the propagation delay of the complete digital system while the mean error for the used gates in this system is 2.5% when compared to SPICE-based simulations.

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Section: Mostly Input Dependentmentioning

confidence: 95%

Scalable Gate-Level Models for Power and Timing Analysis

Badaroglu

Plas

Wambacq

et al. 2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Moreover, the model does not describe the subthreshold region and therefore on/off drain current tradeoffs cannot be thoroughly analyzed. Lots of research work on the delay model of CMOS Inverter has been proposed [6,8,9,12].…”

Section: Related Workmentioning

confidence: 99%

Comprehensive analysis of delay in UDSM CMOS circuits

Samanta

2011

2011 International Conference on Electronics, Communication and Computing Technologies

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In this paper, we have developed a simple and accurate delay model for any Ultra Deep Sub-micron (UDSM) CMOS inverter, NAND2 & NOR2 based on n th power law of MOSFET model when the channel length is of the order of less than or equal to 90nm. We have taken all the parameters from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects such as Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), etc which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 input CMOS NAND and NOR gate. Our result is better than nth power law and Cadence (UMC90nm) simulation result with respect to both quality and estimation time. Our proposed model gives an average error of only 3.63% with compare to Cadence Simulation result.

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“…Hedenstierna (1987) und Jeppson (1994) leiteten analytische Zusammenhänge mit heute nicht mehr zutreffenden Transistormodellen ab. Weitere Ansätze beruhten auf der Vernachlässigung des InverterQuerstroms (Sakurai, 1990;Vemuru, 1994;Dutta, 1995), welche brauchbare Ergebnisse nur für kurze, d.h. schnelle Eingangsflanken lieferten. Mittels stückweise linearer Näherung des Inverter-Querstroms (Hirata, 1996;Bisdounis, 1998Bisdounis, , 2000 (Sakurai, 1990) ist ein derartiges Modell, das sich durch seine mathematisch einfache Beschreibung und einer für digitale Schaltungen brauchbaren Genauigkeit auszeichnet:…”

Section: Introductionunclassified

Analytische Modellierung des Zeitverhaltens und der Verlustleistung von CMOS-Gattern

Geißler¹,

Pfleiderer²

2003

Adv. Radio Sci.

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Zusammenfassung. In modernen CMOS-In modern CMOS-technologies the gate delay, output transition time and the short-circuit current depend on the capacitive load as well as on the input transition time. Today's technology libraries use table models with 25 or more samples for these dependencies. Intermediate values have to be calculated through interpolation. Attempts to derive analytical models are based on neglecting the short-circuit current or approximating it by piecewise linear functions. The approach shown in this paper provides an approximate solution for the differential equation describing the dynamic behavor of an inverter circuit. It includes the influence of both transistor currents and a single load capacitance. The required values for timing and power analysis can be calculated with a small set of technology parameters for an arbitrary designed inverter. Compared to reference values extracted fromCorrespondence to: R. Geißler (richard.geissler@e-technik.uni-ulm.de) SPICE simulations, the model achieves a typical precision of 5%.

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A comprehensive delay model for CMOS inverters

Cited by 93 publications

References 7 publications

Scalable Gate-Level Models for Power and Timing Analysis

Scalable Gate-Level Models for Power and Timing Analysis

Comprehensive analysis of delay in UDSM CMOS circuits

Analytische Modellierung des Zeitverhaltens und der Verlustleistung von CMOS-Gattern

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