A 16.8 Gbps/channel single-ended transceiver for SiP-based DRAM interface on silicon carrier channel is proposed in this paper. A transmitter, receiver, and channel are all included in a single package as SiP. A current mode 4:1 MUX with 1-tap feed-forward equalizer (FFE) is used as a serializer, and this 4:1 MUX uses 25% duty clock to prevent short circuit current when consecutive 2-phase clocks overlap. Additionally, an open drain output driver with asynchronous type 1-tap FFE is used in the transmitter. Because of its small physical size, a common mode variation of Si-carrier channel from process variation is more serious than that of conventional PCB. This common mode variation degrades bit error rates (BER) at single-ended signaling. To obtain effective single-ended signaling on Si-carrier channel, a source follower-based continuous time linear equalizers and selfgenerator with training algorithm on the receiver are proposed. An implemented Si-carrier channel uses meshed layer as a reference to reduce insertion loss. A BER less than 1e-12 is achieved in 65 nm CMOS and the power efficiency of the transceiver is 5.9 pJ/bit with 120 terminations at each transceiver side.Index Terms-Bit error rates (BER) and 120 terminations, continuous time linear equalizer (CTLE), feed-forward equalizer (FFE), selfgenerator, single-ended transceiver, SiP-based DRAM interface.
A 16.8Gbps/channel single ended transceiver for SiP based DRAM interface on silicon carrier channel is presented. A transmitter, receiver, and channel are all included in a single package. On the transmitter, 1 tap FFEs are used in 4:1 MUX and in output driver. On the receiver, source follower based CTLEs and self Vref generator are used for obtaining effective single ended signaling on Si-carrier channel. A BER that is less than 1e-12 is achieved in 65nm CMOS. The power efficiency of the transceiver is 5.9pJ/bit with 120Ω terminations at each transceiver side.
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