A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications

Hwang, Kyu-Dong; Kim, Boram; Byeon, Sangyeon; Kim, Kyuyoung; Kwon, Daehan; Lee, Hyun-Bae; Lee, Geun-Il; Yoon, Sang-Sic; Cha, Jinyoup; Jang, Soo-Young; Lee, Seunghun; Joo, Yong-Suk; Lee, Gang-Sik; Xi, Sung-Soo; Lim, Sojung; Chu, Kyung-Ho; Cho, Joohwan; Chun, Junhyun; Oh, Jae‐Eung; Kim, Jinkook; Lee, Seok-Hee

doi:10.1109/isscc.2018.8310258

Cited by 18 publications

(2 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Another example is memory bus systems such as [6,7], that serve as data channels in very dense parallel buses, where the design cost, power, and absolute delay are more prioritized.…”

Section: Introductionmentioning

confidence: 99%

System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks

Song¹,

Sui²

2019

Electronics

View full text Add to dashboard Cite

This decade has witnessed wide use of data-driven systems, from multimedia to scientific computing, and in each case quality data movement infrastructure is required, many with SerDes as a cornerstone. On the one hand, HPC and machine learning cloud infrastructure carry exabytes of data in a year through the backplanes of data centers. On the other hand, the growing need for edge computing in the IoT places a tight envelope on the energy per bits. In this survey, we give a system level overview of the common design challenges in implementing SerDes solutions under different scenarios and propose simulation methods benefiting from advanced machine learning techniques. Preliminary results with the proposed simulation platform are demonstrated and analyzed through machine learning based design methodologies.

show abstract

“…Another example is memory bus systems such as [6,7], that serve as data channels in very dense parallel buses, where the design cost, power, and absolute delay are more prioritized.…”

Section: Introductionmentioning

confidence: 99%

System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks

Song¹,

Sui²

2019

Electronics

View full text Add to dashboard Cite

show abstract

“…The diversity of high-speed I/O standards for DRAM requires an automated way of doing production tests over a variety of channels [1,2,3,4,5,6,7]. DRAM standards, such as DDR4, LPDDR4, GDDR5, and HBM address different application-specific needs in PCs, mobile devices, graphics processors, and artificial intelligence (AI) accelerators, respectively [8,9,10,11], and use different I/O channels whose loss characteristics span a wide variety, as shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

Kim

2019

IEICE Electron. Express

View full text Add to dashboard Cite

This paper describes a transmitter that can emulate a wide variety of frequency-dependent loss characteristics of high-speed dynamic random-access memory (DRAM) channels, with an aim to facilitate an automated test procedure for a DRAM interface, which does not require physical reconfiguration of channels. Specifically, the proposed transmitter can generate the waveform of an NRZ data stream that has experienced adjustable amounts of skin-effect loss and dielectric loss in electrical channels. To save the hardware cost of implementing a high-speed, high-resolution digital-to-analog converter, the transmitter constructs the waveform using a set of logarithmic and exponential basis functions, each of which is implemented using a pseudo-logarithmic amplifier and lowbandwidth amplifier with adjustable gain and bandwidth, respectively. The prototype chip, fabricated in a 65-nm CMOS process, occupies an area of 5200 µm 2 and operates over 1.4-7 Gbps while dissipating 38 mW at 7 Gbps. It is demonstrated that the implemented transmitter can emulate 10-40"-long microstrip lines on an FR4 grade material with a peak error less than 12.5% in the pulse response.

show abstract

GAHLS: an optimized graph analytics based high level synthesis framework

Xiao,

Nazarian,

Bogdan

2023

Sci Rep

View full text Add to dashboard Cite

The urgent need for low latency, high-compute and low power on-board intelligence in autonomous systems, cyber-physical systems, robotics, edge computing, evolvable computing, and complex data science calls for determining the optimal amount and type of specialized hardware together with reconfigurability capabilities. With these goals in mind, we propose a novel comprehensive graph analytics based high level synthesis (GAHLS) framework that efficiently analyzes complex high level programs through a combined compiler-based approach and graph theoretic optimization and synthesizes them into message passing domain-specific accelerators. This GAHLS framework first constructs a compiler-assisted dependency graph (CaDG) from low level virtual machine (LLVM) intermediate representation (IR) of high level programs and converts it into a hardware friendly description representation. Next, the GAHLS framework performs a memory design space exploration while account for the identified computational properties from the CaDG and optimizing the system performance for higher bandwidth. The GAHLS framework also performs a robust optimization to identify the CaDG subgraphs with similar computational structures and aggregate them into intelligent processing clusters in order to optimize the usage of underlying hardware resources. Finally, the GAHLS framework synthesizes this compressed specialized CaDG into processing elements while optimizing the system performance and area metrics. Evaluations of the GAHLS framework on several real-life applications (e.g., deep learning, brain machine interfaces) demonstrate that it provides 14.27× performance improvements compared to state-of-the-art approaches such as LegUp 6.2.

show abstract

A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications

Cited by 18 publications

References 3 publications

System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks

System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks

A channel-emulating high-speed transmitter with pseudo-logarithmic and low-bandwidth amplifiers

GAHLS: an optimized graph analytics based high level synthesis framework

Contact Info

Product

Resources

About