25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation

Kim, Kyunghoon; Chae, Joo-Hyung; Yang, Jaehyeok; Kang, Ji-Hyo; Lee, Gang-Sik; Byeon, Sangyeon; Kim, Boram; Kim, Dong-Hyun; Cho, Yeongmuk; Choi, Kangmoo; Park, Hyeongyeol; Ji, Junghwan; Jeong, Sera; Joo, Yong-Suk; Cha, Jae-Hoon; Park, Minsoo; Kim, Hongdeuk; Park, Sijun; Kong, Kyubong; Kim, Sun-Ho; Lee, Sang Kwon; Chun, Junhyun; Kim, Hyungsoo; Cha, Seon-Yong

doi:10.1109/isscc42613.2021.9365844

Cited by 10 publications

(1 citation statement)

References 3 publications

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“…When the encoder is placed in front of the output driver, the data and the driver code are encoded, and then encoded data are sent to the output driver; this can make the output driver configuration simple. However, the propagation delay of the data path increases by the delay of the encoder, increasing the power-supply-induced jitter and deteriorating the output drift characteristics in memory interfaces [14]. The proposed output driver in Figure 5b can improve these issues by removing the encoder.…”

Section: Proposed Pam-4 Transmittermentioning

confidence: 99%

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

et al. 2021

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This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. The ZQ code generator then adaptively selected the appropriate codes depending on the data pattern and delivered them to the output driver; this can improve the level separation mismatch ratio (RLM) while matching the channel impedance. To validate the effectiveness of our approach, a prototype chip with an active area of 0.035 mm2 was fabricated in a 65 nm CMOS process. It achieved the energy efficiency of 3.09 pJ/bit/pin at 18 Gb/s/pin, and its RLM was 0.971 while matching the channel impedance.

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Section: Proposed Pam-4 Transmittermentioning

confidence: 99%

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

et al. 2021

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Circuit‐Level Memory Technologies and Applications based on 2D Materials

Liu

Yang

et al. 2022

Advanced Materials

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random-access memory (DRAMs), static random-access memory (SRAMs), [1] and flash memory, [2] multiple transistors and capacitors are employed to constitute a single functional cell. These functional cells are typically integrated to form a memory array for advanced functionality, miniaturized footprints, low power consumption, and reduced latency. Traditional silicon-based complementary metal-oxidesemiconductor (CMOS) technology has been widely used to build these memory arrays. However, the performance improvement of CMOS-based memory relies on the advance of nanofabrication technology to scale down the feature size of transistors, which is approaching the physical limit. [3] To overcome this bottleneck, emerging memory technologies are brought up as promising supplements to conventional memory devices. [4] These novel types of memory include resistive random-access memory (RRAM), [5,6] ferroelectric RAM (FeRAM), [7] optoelectronic RRAM (ORRAM), [8,9] phase-change memory (PCM), [10] and spin-transfer torque magnetoresistive RAM (STT-MRAM). [11,12] Furthermore, emerging memory devices allow non-von-Neumann architectures that pave the way toward high-performance in-memory computing technology. [13,14] For example, memristive crossbar arrays composed of 1-transistor-1-resistor (1T1R) unit cells can enable in-memory computing and are the most cost-efficient thanks to their two-terminal structure. [15] Advanced 3D monolithic stacking integration also emerges as a promising approach to Memory technologies and applications implemented fully or partially using emerging 2D materials have attracted increasing interest in the research community in recent years. Their unique characteristics provide new possibilities for highly integrated circuits with superior performances and low power consumption, as well as special functionalities. Here, an overview of progress in 2D-material-based memory technologies and applications on the circuit level is presented. In the material growth and fabrication aspects, the advantages and disadvantages of various methods for producing large-scale 2D memory devices are discussed. Reports on 2D-material-based integrated memory circuits, from conventional dynamic random-access memory, static random-access memory, and flash memory arrays, to emerging memristive crossbar structures, all the way to 3D monolithic stacking architecture, are systematically reviewed. Comparisons between experimental implementations and theoretical estimations for different integration architectures are given in terms of the critical parameters in 2D memory devices. Attempts to use 2D memory arrays for in-memory computing applications, mostly on logic-in-memory and neuromorphic computing, are summarized here. Finally, challenges that impede the large-scale applications of 2D-material-based memory are reviewed, and perspectives on possible approaches toward a more reliable system-level fabrication are also given, hopefully shedding some light on future research.

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Energy-Efficient Bus Encoding Techniques for Next-Generation PAM-4 DRAM Interfaces

Lee

Song

et al. 2022

2022 IEEE 40th International Conference on Computer Design (ICCD)

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25.1 A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation

Cited by 10 publications

References 3 publications

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

Circuit‐Level Memory Technologies and Applications based on 2D Materials

Energy-Efficient Bus Encoding Techniques for Next-Generation PAM-4 DRAM Interfaces

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