A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

Kang, Ji-Hyo; Yang, Jaehyeok; Kim, Kyunghoon; Chae, Joo-Hyung; Lee, Gang-Sik; Byeon, Sangyeon; Kim, Boram; Kim, Dong-Hyun; Cho, Yeongmuk; Ji, Junghwan; Jeong, Sera; Cha, Jae-Hoon; Park, Minsoo; Kim, Hongdeuk; Park, Sijun; Kim, Sun-Ho; Jung, Hae-Kang; Jang, Jieun; Lee, Sang Kwon; Kim, Hyungsoo; Cho, Joohwan; Chun, Junhyun; Cha, Seon-Yong

doi:10.1109/jssc.2021.3114205

Cited by 6 publications

(1 citation statement)

References 11 publications

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“…It also gives a big relief from the significant design overhead dealing with mismatches in the amplitude and the phase errors in differential paths, especially when the targeted symbol rate has a UI < 20 ps [32]. However, a single-ended inverter-based architecture is sensitive to power supply noise, which can elevate the power supply induced jitter (PSIJ) [59], [60]. Although this is not required in this work, it can be mitigated with either placing the TIA circuits with its own isolated supply voltage or having a dedicated on-chip low dropout regulator (LDO) [48], [61], [62].…”

Section: B Low-power Design Choices 1) Inverter As a Fundamental Blockmentioning

confidence: 99%

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

Patel

Sharif-Bakhtiar

Carusone

2023

IEEE J. Solid-State Circuits

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A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4-PAM) with −8.2-dBm sensitivity is presented in support for optical receivers required in the next-generation intradata center links. A proposed three-stage TIA is comprised of a shunt-feedback stage followed by digitally programmable continuous-time linear equalizers (CTLEs) and a variable gain amplifier (VGA). Broadband low-noise design is achieved by having the first stage with much lower bandwidth (BW) followed by the proposed BW recovering CTLEs. A low-power design is supported by the inverter-based single-ended architecture with a single-ended-to-pseudo-differential conversion in the last stage. TIA's BW extension is further supported by optimizing the photodiode-to-receiver (PD-to-RX) interconnect and utilizing several inductive peaking techniques. It achieves 63-dB gain, 32-GHz BW, and an average input-referred current noise density of 16.9 pA/ √ Hz while operating at 0.9-V supply and consuming 47-mW power. Opto-electrical measurements are performed on a co-packaged prototype comprised of identical proposed TIAs in CMOS with combinations of various commercial PDs and PD-to-RX interconnect lengths confirming 112-Gb/s 4-PAM reception meeting pre-forward error correction (FEC) symbol error rate (SER) of 4.8 × 10 −4 without any post-equalization. Index Terms-100 Gb/s, 400 GbE, CMOS, co-packaged optical receiver front end, continuous-time linear equalizer (CTLE), fin field effect transistor (FinFET), gigabit Ethernet, inverter, low-noise broadband amplifier, optical communications, PAM-4, transimpedance amplifier (TIA). I. INTRODUCTIONT HE Big Bang of the Internet powering 5G, artificial intelligence (AI), machine learning (ML), video conferencing, the Internet of Things (IoT), and cloud storage applications has continuously increased the demand on the

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Section: B Low-power Design Choices 1) Inverter As a Fundamental Blockmentioning

confidence: 99%

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

Patel

Sharif-Bakhtiar

Carusone

2023

IEEE J. Solid-State Circuits

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13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency

Han,

Lee,

Chae

2024

2024 IEEE International Solid-State Circuits Conference (ISSCC)

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A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

Lee

Baek

Kwon

et al. 2023

IEEE J. Solid-State Circuits

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A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

Cited by 6 publications

References 11 publications

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes

13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ

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