INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0740-7475Although parity prediction arithmetic operators are compatible with systems checked by parity codes, they are not secure against single faults. The authors determine the necessary conditions for fault secureness and derive designs embodying these conditions

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Physical attacks focus on extracting information from internal parts of IC's. One way to achieve this is by means of connecting probes to wires, so that the content of internal buses and registers can be revealed. Protection against this type of attacks exists, but usually is bulky and expensive, e.g. the shielding of secured areas. This paper presents a novel in-circuit countermeasure that is cheap and can easily be integrated in existing designs to detect probing attempts. It is based on a ring oscillator that operates over coupled lines in a differential mode. When the loading of one of the lines is unbalanced over a tolerance margin, an impulse is generated and integrated over time. If the integration surpasses a given threshold an alarm signal is activated. Simulations show the stability of the detector over a range of temperature and supply voltage variations

Abstract-Microprobing allows intercepting data from onchip wires as well as injecting faults into data or control lines. This makes it a commonly used attack technique against security-related semiconductors, such as smart card controllers. We present the low area probing detector (LAPD) as an efficient approach to detect microprobing. It compares delay differences between symmetric lines such as bus lines to detect timing asymmetries introduced by the capacitive load of a probe. Compared with state-of-the-art microprobing countermeasures from industry, such as shields or bus encryption, the area overhead is minimal and no delays are introduced; in contrast to probing detection schemes from academia, such as the probe attempt detector, no analog circuitry is needed. We show the Monte Carlo simulation results of mismatch variations as well as process, voltage, and temperature corners on a 65-nm technology and present a simple reliability optimization. Eventually, we show that the detection of state-of-the-art commercial microprobes is possible even under extreme conditions and the margin with respect to false positives is sufficient.

Aquesta és una còpia de la versió author's final draft de l'article Unpredictable bits generation based on RRAM parallel configuration publicat a IEEE electron device letters.

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In this paper, we present a new scan-path structure for improving the security of systems including scan paths, which normally introduce a security critical information leak channel into a design. Our structure, named differential scan path (DiSP), divides the internal state of the scan path in two sections. During the shift-out operation, only subtraction of the two sections is provided. Inferring the internal state from this subtraction requires much guesswork that increases exponen-tially with scan path length while the resulting fault coverage is only marginally altered. Subtraction does not preserve parity, thus avoiding attacks using parity information. The structure is simple, needs little area and does not require unlocking keys. Through implementing the DiSP in an elliptic curve crypto-graphic coprocessor, we demonstrate how easily it can be inte-grated into existing design tools. Simulations show that test effectiveness is preserved and that the internal state is effec-tively hidden.Postprint (published version