Low power BIST by filtering non-detecting vectors

Manich, Salvador; Gabarró, A.; Lopez, M.; Figueras, Joan; Girard, Patrick; Guiller, L.; Landrault, C.; Pravossoudovitch, S.; Teixeira, Paulo Fonseca; Santos, M.B.

doi:10.1109/etw.1999.804524

Cited by 28 publications

(23 citation statements)

References 8 publications

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“…Several methods were proposed for low-power BIST using test vector inhibiting [14], [15], [16] to filter out some nondetecting subsequences of a pseudorandom test set generated by an LFSR. These methods result in more power reduction, but have high area overhead.…”

Section: Circuit-independent Structurementioning

confidence: 99%

“…The comparison between LT-LFSR and other techniques such as those proposed in [14], [15], [16] is not feasible since those are conceptually different. These techniques try to filter the nondetecting vectors that result in reduction in the average test power and may also reduce the peak power.…”

Section: Simulations Setup and Implementationmentioning

confidence: 99%

“…The technique proposed in [17] reduces the power during test by suppressing the output switch during shifting. The techniques proposed here and in [14], [15], [16] are different from that in [17] since these techniques work on test patterns. Compared to all of these techniques, our proposed technique reduces the switching activity among patterns and this has given us a significant reduction in both peak and average power.…”

Section: Simulations Setup and Implementationmentioning

confidence: 99%

“…The authors of [13] proposed a method to select an LFSR's seed to reduce the lowest energy consumption using a simulated-annealing algorithm. Test vector inhibiting techniques [14], [15], [16] filter out some nondetecting subsequences of a pseudorandom test set generated by an LFSR. These architectures apply the minimum number of test vectors required to attain the desired fault coverage and therefore reduce power.…”

Section: Prior Workmentioning

confidence: 99%

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Low-Transition Test Pattern Generation for BIST-Based Applications

Nourani

Tehranipoor

Ahmed

2008

IEEE Trans. Comput.

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Abstract-A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during test by reducing the transitions among patterns. Transitions are reduced in two dimensions: 1) between consecutive patterns (fed to a combinational only circuit) and 2) between consecutive bits (sent to a scan chain in a sequential circuit). LT-LFSR is independent of circuit under test and flexible to be used in both BIST and scan-based BIST architectures. The proposed architecture increases the correlation among the patterns generated by LT-LFSR with negligible impact on test length. The experimental results for the ISCAS'85 and '89 benchmarks confirm up to 77 percent and 49 percent reduction in average and peak power, respectively.

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Section: Circuit-independent Structurementioning

confidence: 99%

Section: Simulations Setup and Implementationmentioning

confidence: 99%

Section: Simulations Setup and Implementationmentioning

confidence: 99%

Section: Prior Workmentioning

confidence: 99%

See 2 more Smart Citations

Low-Transition Test Pattern Generation for BIST-Based Applications

Nourani

Tehranipoor

Ahmed

2008

IEEE Trans. Comput.

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“…Many approaches have been proposed for minimizing spurious transitions during test application at logic level of abstraction [6,8,10,16,20,23,27,28]. Despite their efficiency, logic level approaches need to be combined with solutions at higher levels of abstraction due to the complexity of the state of the art designs.…”

Section: Introductionmentioning

confidence: 99%