Fault-secure parity prediction arithmetic operators

Nicolaidis, M.; Duarte, Ricardo de Oliveira; Manich, Salvador; Figueras, Joan

doi:10.1109/54.587743

Cited by 72 publications

(34 citation statements)

References 5 publications

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“…To assist us in selecting the assertions to be included in the assertion checker, we use transient fault simulations using sample segments of real applications and take into consideration only the faults which propagate all the way to the architectural states of the processor. This differs from the experimental methodology followed in almost all previous CED schemes proposed [1], [3], [5], [8], [11], [12], where random vectors are used as inputs of the combinational circuits and all the faults which propagate to the outputs of the combinational portion are considered important. The methodology followed in this paper is similar to the one used in [6] for logic derating.…”

Section: Overviewmentioning

confidence: 65%

“…For control logic circuits, codeword based schemes have been proposed. Codes like parity [8], [11], [12], Berger [3] and Bose-Lin [1] are predicted for the outputs of the circuit and the codes of real-time outputs are matched against the predicted codes. These techniques for control logic circuits are viable for mission critical applications where reliability is of primary concern and area, timing and power take second place.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A low-cost concurrent error detection technique for processor control logic

Vemu¹,

Abraham²,

Patil³

et al. 2008

2008 Design, Automation and Test in Europe

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show abstract

Section: Overviewmentioning

confidence: 65%

Section: Introductionmentioning

confidence: 99%

A low-cost concurrent error detection technique for processor control logic

Vemu¹,

Abraham²,

Patil³

et al. 2008

2008 Design, Automation and Test in Europe

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show abstract

“…[36][37][38][39][40]) can be more lightweight and offer less expensive solutions. In the present paper we show that even with this basic and nonoptimized detection scheme the rollback recovery will require less overhead than feed-forward fault-tolerant techniques.…”

Section: Detection Blockmentioning

confidence: 99%

Fault-tolerant sub-lithographic design with rollback recovery

Naeimi

DeHon

2008

Nanotechnology

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Shrinking feature sizes and energy levels coupled with high clock rates and decreasing node capacitance lead us into a regime where transient errors in logic cannot be ignored. Consequently, several recent studies have focused on feed-forward spatial redundancy techniques to combat these high transient fault rates. To complement these studies, we analyze fine-grained rollback techniques and show that they can offer lower spatial redundancy factors with no significant impact on system performance for fault rates up to one fault per device per ten million cycles of operation (P f = 10 −7 ) in systems with 10 12 susceptible devices. Further, we concretely demonstrate these claims on nanowire-based programmable logic arrays. Despite expensive rollback buffers and general-purpose, conservative analysis, we show the area overhead factor of our technique is roughly an order of magnitude lower than a gate level feed-forward redundancy scheme.

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“…Several concurrent error detectable adders using parity bits have been proposed [8]- [11]. In [8], a fault-secure ripple carry adder is shown.…”

Section: Introductionmentioning

confidence: 99%

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

Kito

Takagi

2013

IEICE Trans. Inf. & Syst.

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SUMMARYWe propose a low-overhead fault-secure parallel prefix adder. We duplicate carry bits for checking purposes. Only one half of normal carry bits are compared with the corresponding redundant carry bits, and the hardware overhead of the adder is low. For concurrent error detection, we also predict the parity of the result. The adder uses paritybased error detection and it has high compatibility with systems that have parity-based error detection. We can implement various fault-secure parallel prefix adders such as Sklansky adder, Brent-Kung adder, Han-Carlson adder, and Kogge-Stone adder. The area overhead of the proposed adder is about 15% lower than that of a previously proposed adder that compares all the carry bits. key words: parity prediction, parallel prefix adder, fault secure, carry-bit duplication

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Fault-secure parity prediction arithmetic operators

Cited by 72 publications

References 5 publications

A low-cost concurrent error detection technique for processor control logic

A low-cost concurrent error detection technique for processor control logic

Fault-tolerant sub-lithographic design with rollback recovery

Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication

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