Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity

Girard, Patrick; Guiller, L.; Landrault, C.; Pravossoudovitch, S.; Figueras, Joan; Manich, Salvador; Teixeira, Paulo Fonseca; Santos, M.B.

doi:10.1109/iscas.1999.777817

Cited by 42 publications

(10 citation statements)

References 12 publications

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“…Power-Driven Control of LFSR. The authors of [13] proposed a method to select an LFSR's seed to reduce the lowest energy consumption using a simulated-annealing algorithm. Test vector inhibiting techniques [14], [15], [16] filter out some nondetecting subsequences of a pseudorandom test set generated by an LFSR.…”

Section: Prior Workmentioning

confidence: 99%

Low-Transition Test Pattern Generation for BIST-Based Applications

Nourani

Tehranipoor

Ahmed

2008

IEEE Trans. Comput.

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Abstract-A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during test by reducing the transitions among patterns. Transitions are reduced in two dimensions: 1) between consecutive patterns (fed to a combinational only circuit) and 2) between consecutive bits (sent to a scan chain in a sequential circuit). LT-LFSR is independent of circuit under test and flexible to be used in both BIST and scan-based BIST architectures. The proposed architecture increases the correlation among the patterns generated by LT-LFSR with negligible impact on test length. The experimental results for the ISCAS'85 and '89 benchmarks confirm up to 77 percent and 49 percent reduction in average and peak power, respectively.

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Section: Prior Workmentioning

confidence: 99%

Low-Transition Test Pattern Generation for BIST-Based Applications

Nourani

Tehranipoor

Ahmed

2008

IEEE Trans. Comput.

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“…LFSR tuning modifies the state transitions of the LFSR such that only the useful vectors are generated according to a desired sequence [32]. To reduce such energy consumption, a mapping logic is designed in [33] which modifies the state transitions of the LFSR such that only the useful vectors are generated according to a desired sequence.…”

Section: By Generating the Useful Vectors Onlymentioning

confidence: 99%

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

2011

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Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.

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“…The technique generates random but highly correlated neighboring bits in the scan chain, reducing the number of transitions and, thus, the average power. Authors in [10] proposed a method to select an LFSR's seed to reduce the lowest energy consumption using a simulated-annealing algorithm. Test vector inhibiting techniques [11] [12] [13] filter out some non-detecting subsequences of a pseudorandom test set generated by an LFSR.…”

Section: A Prior Workmentioning

confidence: 99%

Low Transition LFSR for BIST-Based Applications

Tehranipoor

Nourani

Ahmed

2005

14th Asian Test Symposium (ATS'05)

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Abstract-This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within random test pattern and between consecutive patterns. In other words, transitions are reduced in two dimensions, i.e. between consecutive patterns (fed to a combinational circuit) and consecutive bits (sent to a scan chain). LT-LFSR is independent of circuit under test and flexible to be used for both BIST and scan-based BIST architectures. The experimental results for ISCAS'85 and '89 benchmarks, confirm up to 77% and 49% reduction in average and peak power, respectively.

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Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity

Cited by 42 publications

References 12 publications

Low-Transition Test Pattern Generation for BIST-Based Applications

Low-Transition Test Pattern Generation for BIST-Based Applications

Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey

Low Transition LFSR for BIST-Based Applications

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