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The 64b PowerPC RISC microprocessor previously described is migrated from a 0.22µm SOI technology to a 0.18µm SOI technology [1]. Key features of the 0.77 scaled 1.5V technology are 0.08µm NFET channel lengths, 7 layer Cu metallization with low-e dielectric, low dose SOI substrate for improved material quality and productivity, and local interconnect. Dual gate oxide provides high I/O voltage compatibility. As this chip is a migration only 6 levels of metal and stacked devices for high voltage I/O were used.

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Silicon-on-insulator (SOI) technology allows higher performance than bulk technology. However, the floating body effect in SOI devices poses challenges via history effects, bipolar currents, and lower noise margins on dynamic circuits. This 64b adder is used to compute the effective address in a PowerPC TM processor. Particular emphasis is on design issues, advantages resulting from unique SOI device structures, and the techniques for controlling floating body effect in partially-depleted devices. Adder performance comparison is shown for bulk CMOS, first-generation SOI CMOS, and-second generation SOI CMOS.High-speed microprocessor cycle time is limited by a number of critical paths, one of which involves a cache memory access initiated by a load or store instruction. For instance, an instruction of the form: lwaux RT, RC, RB (PowerPC TM load word Algebraic with update indexed) requires the value in register RC to be added to the value in register RB to produce the effective address (EA). The effective address is used to access the translation lookaside buffer (TLB) and the cache memory (Figure 17.1.1).