A 2nd generation 440 ps SOI 64 b adder

Abstract

Silicon-on-insulator (SOI) technology allows higher performance than bulk technology. However, the floating body effect in SOI devices poses challenges via history effects, bipolar currents, and lower noise margins on dynamic circuits. This 64b adder is used to compute the effective address in a PowerPC TM processor. Particular emphasis is on design issues, advantages resulting from unique SOI device structures, and the techniques for controlling floating body effect in partially-depleted devices. Adder performance comparison is shown for bulk CMOS, first-generation SOI CMOS, and-second generation SOI CMOS.High-speed microprocessor cycle time is limited by a number of critical paths, one of which involves a cache memory access initiated by a load or store instruction. For instance, an instruction of the form: lwaux RT, RC, RB (PowerPC TM load word Algebraic with update indexed) requires the value in register RC to be added to the value in register RB to produce the effective address (EA). The effective address is used to access the translation lookaside buffer (TLB) and the cache memory (Figure 17.1.1).

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

“…Increased understanding of how SOI devices behave, and possible solutions to their quirks has lead to a wider acceptance of SOI in the VLSI community. Recently, SOI has been used in a number of high-end microprocessor designs, e.g., IBM Power PC [11], [12], HP-PA 8700 [13], and others [14], [15], as well as other high-performance logic circuits [16]- [18]. The manufacturing process of SOI is very similar to that of bulk CMOS.…”

SOI technology for the GHz era

“…The SOI-induced uncertainty in delay, while not negligible, is no larger than other sources of uncertainty on a chip, and can be managed in a similar fashion [13]. At the microprocessor level, the history effect in SOI is much less noticeable [13][14][15] than the uncertainty in delay of a simple circuit block in SOI (i.e., an inverter or a NOR stage). The processor cycle time (or the chip frequency) is usually determined by a few cyclelimiting paths (i.e., the longest latch-to-latch delay).…”

“…The other floating-body effect is "passgate leakage," or the reduction in the device V T when the body charges to very high voltage, as high as V DD [9]. A number of techniques have been developed to minimize the impact of passgate leakage [14,16,17], and most of the effort in mapping bulk-Si circuits to SOI is spent on fixing circuits affected by it [13,15]. The challenge of circuit design in SOI is to properly screen every circuit type for passgate leakage (functionality, noise performance, and timing) [14,16,17].…”

Sub-500 ps 64 b ALUs in 0.18 μm SOI/bulk CMOS: Design & scaling trends

“…A direct port of this design to a comparable SOI technology [3] results in a 16% increase in performance ( Figure 20 where the maximum interstage load is 750µm of interconnect, spanning 32 carry-merge bit slices. The 16% speedup is lower than that reported in [4]. This is attributable to the aggressive reduction of junction capacitances in the contending bulk CMOS process [3].…”