A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects

Aipperspach, A.G.; Allen, D.H.; Cox, D.; Phan, N.; Storino, S.N.

doi:10.1109/4.799846

Cited by 46 publications

(18 citation statements)

References 1 publication

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“…This problem is identical to that of register file and SRAM bit lines [15], [16]. A number of solutions to this problem have been proposed, with the most widely used probably being domino "burn-in keepers" [17], [18], which adjust the keeper strength in the worst case, i.e., during circuit burn-in.…”

Section: A Xscale Embedded Microprocessor Cache Tagsmentioning

confidence: 98%

Low-power high-performance nand match line content addressable memories

Chaudhary

Clark

2006

IEEE Trans. VLSI Syst.

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Content addressable memory (CAM) is used in fully associative VLSI lookup circuits for cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address comparison. In this paper, the use of dynamic NAND match lines is investigated and compared to conventional NOR match lines in cache applications. To achieve high speed, a hierarchical match line is used. The dynamic stack charge-sharing noise immunity, speed, and actual power savings over a conventional NOR match line are investigated using benchmark data. While random patterns are often used when benchmarking CAM match line power, it is shown to be optimistic compared to address trace data, since addresses are highly correlated. It is also shown that proper address input ordering can provide additional power savings. A simple model for the power in dynamic circuit stacks is derived and compared to power simulation data. Additionally, impact on cache tag area and the scaling of the NAND stack to future processes is described.Index Terms-Cache tag, content addressable memory (CAM), domino power, NAND match line.

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Section: A Xscale Embedded Microprocessor Cache Tagsmentioning

confidence: 98%

Low-power high-performance nand match line content addressable memories

Chaudhary

Clark

2006

IEEE Trans. VLSI Syst.

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“…The proposed approach refers to silicon CMOS deep-submicrometer technologies, where-according to [10]-the minimal logic gate delay is approximated by , where is a technology-dependent parameter. 1 is near to for , so that in the following, we use . Actually, silicon-on-insulator (SOI) technology could be a valid alternative target, as the short-channel scaling effects could be partially solved by SOI [1], [21]; however, the present version 1 According to [10], the MOSFET saturation current is I = qv wC (V 0 v 0 v ) and the minimal gate delay is well ap- of this work addresses CMOS as the most used microprocessor fabrication technology.…”

Section: A Assumptionsmentioning

confidence: 98%

“…1 is near to for , so that in the following, we use . Actually, silicon-on-insulator (SOI) technology could be a valid alternative target, as the short-channel scaling effects could be partially solved by SOI [1], [21]; however, the present version 1 According to [10], the MOSFET saturation current is I = qv wC (V 0 v 0 v ) and the minimal gate delay is well ap- of this work addresses CMOS as the most used microprocessor fabrication technology. The total power consumption of any digital system is [4], where and are the short-circuit and the leakage current, respectively.…”

Section: A Assumptionsmentioning

confidence: 98%

Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design

Olivieri

2002

IEEE Trans. VLSI Syst.

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This brief paper provides a quantitative understanding of the relations among supply-voltage scaling, sustainable cycle time, pipeline depth, instruction-level parallelism, and power dissipation. Starting from simple well-established formulas, the analysis show that there is an optimal sizing of the target supply voltage and pipe stage complexity to minimize power under a performance constraint. The verification of the model on five real processors is reported and discussed, and the application to an ideal microprocessor design or redesign is illustrated

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“…SOI has becomes matured technology and offers several advantages compared to bulk MOSFET such as reduced junction capacitance, immunity to latch up, and less prone to soft-errors etc [5]. Due to its advantages over the bulk, SOI is being used commercially for low power and high speed applications [6]- [8].…”

Section: Introductionmentioning

confidence: 99%

Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence

Yadav

Dutta

Sirohi

et al. 2016

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)

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In this paper, a physics based impact ionization model for silicon MOSFETs is proposed. The proposed impact ionization model specially addresses the physics for the low Vds or subband gap impact ionization (thermally assisted) along with the conventional (channel field assisted) high Vds impact ionization. The proposed model is implemented in industry standard BSIMSOI model and verified by comparison with experimental data of partially depleted silicon-on-insulator MOSFET. Model shows excellent agreement with the experimental data for low as well as high Vds impact ionization. The proposed unified impact ionization model shows improved convergence problem in standard test circuit simulation.

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A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects

Cited by 46 publications

References 1 publication

Low-power high-performance nand match line content addressable memories

Low-power high-performance nand match line content addressable memories

Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design

Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence

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