A 660 MHz 64b SOI processor with Cu interconnects

Buchholtz, T.C.; Aipperspach, G.; Cox, D.; Phan, N.; Storino, S.N.; Strom, J.; Williams, R.R.

doi:10.1109/isscc.2000.839703

Cited by 6 publications

(7 citation statements)

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“…Increased understanding of how SOI devices behave, and possible solutions to their quirks has lead to a wider acceptance of SOI in the VLSI community. Recently, SOI has been used in a number of high-end microprocessor designs, e.g., IBM Power PC [11], [12], HP-PA 8700 [13], and others [14], [15], as well as other high-performance logic circuits [16]- [18]. The manufacturing process of SOI is very similar to that of bulk CMOS.…”

Section: A Silicon-on-insulator (Soi)mentioning

confidence: 99%

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Karandikar

Sapatnekar

2003

IEEE Trans. VLSI Syst.

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We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is silicon-on-insulator (SOI). SOI devices exhibit an effect known as parasitic bipolar effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid PBE, such as transistor reordering, altering the way that transistors are organized into gates, and adding pMOS discharge transistors. We minimize the total cost of implementation, which includes discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors required by 53% and reduces the size of the final solution by 6.3% on average. We compare our results with a modification of a current technology mapping algorithm for bulk CMOS domino logic that reduces the cost of the final solution and find that our algorithm outperforms this method.

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Section: A Silicon-on-insulator (Soi)mentioning

confidence: 99%

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Karandikar

Sapatnekar

2003

IEEE Trans. VLSI Syst.

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“…Among the phenomena contributing to uncertainty in a bulk-Si design ( Table 2) are intrachip process variation (about 15-20% of gate delay); delay variation caused by top vs. bottom switching devices in NAND gates, or the number of simultaneous "1"s arriving at a NOR gate (about 20 -35%); on-chip circuit supply voltage (V DD ) variations (about 10%), and temperature variations (on-chip and ambient, which can cause 10 -20% change in delay). The SOI-induced uncertainty in delay, while not negligible, is no larger than other sources of uncertainty on a chip, and can be managed in a similar fashion [13]. At the microprocessor level, the history effect in SOI is much less noticeable [13][14][15] than the uncertainty in delay of a simple circuit block in SOI (i.e., an inverter or a NOR stage).…”

Section: Figurementioning

confidence: 99%

“…The SOI-induced uncertainty in delay, while not negligible, is no larger than other sources of uncertainty on a chip, and can be managed in a similar fashion [13]. At the microprocessor level, the history effect in SOI is much less noticeable [13][14][15] than the uncertainty in delay of a simple circuit block in SOI (i.e., an inverter or a NOR stage). The processor cycle time (or the chip frequency) is usually determined by a few cyclelimiting paths (i.e., the longest latch-to-latch delay).…”

Section: Figurementioning

confidence: 99%

“…The other floating-body effect is "passgate leakage," or the reduction in the device V T when the body charges to very high voltage, as high as V DD [9]. A number of techniques have been developed to minimize the impact of passgate leakage [14,16,17], and most of the effort in mapping bulk-Si circuits to SOI is spent on fixing circuits affected by it [13,15]. The challenge of circuit design in SOI is to properly screen every circuit type for passgate leakage (functionality, noise performance, and timing) [14,16,17].…”

Section: Figurementioning

confidence: 99%

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SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

173

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Silicon-on-insulator (SOI) CMOS offers a 20-35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-m generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-m generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

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“…A number of high end microprocessor designs have recently been implemented in SOI, e.g. HP-PA 8700 [5], IBM Power PC [6][7] [8], and others [9] [10].…”

Section: Silicon-on-insulatormentioning

confidence: 99%

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Karandikar

Sapatnekar

2001

Proceedings of the 38th Conference on Design Automation - DAC '01

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We present a technology mapping algorithm for implementing a random logic gate network in domino logic. The target technology of implementation is Silicon on Insulator (SOI). SOI devices exhibit an effect known as Parasitic Bipolar Effect (PBE), which can lead to incorrect logic values in the circuit. Our algorithm solves the technology mapping problem by permitting several transformations during the mapping process in order to avoid the PBE, such as transistor reordering, altering the way transistors are organized into gates, and adding pmos discharge transistors. We minimize the total cost of implementation, which includes the discharge transistors required for correct functioning. Our algorithm generates solutions that reduce the number of discharge transistors needed by 44.23%, and reduces the size of the final solution by 11.66% on average.

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A 660 MHz 64b SOI processor with Cu interconnects

Cited by 6 publications

References 0 publications

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

SOI technology for the GHz era

Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect

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