An experimental general purpose program based on ICD has been created to aid in the design of bipolar array chips. The program consists of a unique automated set of tools that verify the logic function of every chip circuit, determine signal noise margin, and reliability guideline checking for contact studs. The program was originally developed as part of analog and logic design verification tools to audit the design of a 48K-bit bipolar array cache chip prior to release to manufacturing. The analytic tools used consist of the use of a Semi -Di rect method of analysis, a Gray algorithm, and recognition of diffmntial pairs to minimize the number of simulations (DC reruns), and a set of techniques to take into account the peculiarities of bipolar circuits, such as emitter and collector dots, input output loading conditions, differential pairs and the presence of a mixture of digital, sequential, and analog circuits. As a result, the design verification of 60 distinct circuits (books) of the 48K chip took less than 3 CPU minutes on an IBM 3090 computer. This included, among other things, conducting 2" DC simulations or reruns of each book, where n is the number of inputs or fan-ins. Furthermore, output behavioral models representing the basic chip circuits were used as basic leaf models in HLSIM, a Hierarchical Logic Simulator, which was used to simulate the whole 48K-bit array.
SummaryThe design of any VLSI chip is at a minimum a very complex task. Chip requirements are typically simple, consisting of the number of bits required, read/write organization, and performance. The realization of the
HLSIM is an APL Hierarchical Logic SlMulator that can deal with nested models. The program has all the facilities to handle large VLSI circuits with complicated sequential logic, including full chip simulation. The paper discusses two major programs: an analog to digital netlist converter and a new digital simulator implemented in APL (A Programming Language. APL is a natural environment for logic simulators, especially when its powerhl APL nested array facilities are wed). The netlist converter takes a hierarchical analog netlist and supplementary files IEEE VLSl TEST SYMPOSIUM 1992 0-7803-0623-6/92 $3.00 @ 1992 IEEE Paper 17.3
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides a complete design solution from logic to layout for regularly structured circuits. The STAG circuit tuning constraints are a key component of the methodology. The tuning contraints first guide a SPICE-level tuner to a violation free region in the design space. Secondly, the tuning methodology provides flexibility for targeting a variety of design contraints and objectives. Design examples illustrate STAG's ability for fast turnaround time as well as for high performance and timing critical random logic.
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