This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metaloxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.

Single-walled carbon nanotubes (SWCNTs) have been shown to exhibit excellent electrical properties, such as ballistic transport over several hundred nanometers at room temperature. Field-effect transistors (FETs) made from individual tubes show dc performance specifications rivaling those of state-of-the-art silicon devices. An important next step is the fabrication of integrated circuits on SWCNTs to study the high-frequency ac capabilities of SWCNTs. We built a five-stage ring oscillator that comprises, in total, 12 FETs side by side along the length of an individual carbon nanotube. A complementary metal-oxide semiconductor-type architecture was achieved by adjusting the gate work functions of the individual p-type and n-type FETs used.