HLSIM-a new hierarchical logic simulator in APL

Abstract

HLSIM is an APL Hierarchical Logic SlMulator that can deal with nested models. The program has all the facilities to handle large VLSI circuits with complicated sequential logic, including full chip simulation. The paper discusses two major programs: an analog to digital netlist converter and a new digital simulator implemented in APL (A Programming Language. APL is a natural environment for logic simulators, especially when its powerhl APL nested array facilities are wed). The netlist converter takes a hierarchical analog netlist and supplementary files IEEE VLSl TEST SYMPOSIUM 1992 0-7803-0623-6/92 $3.00 @ 1992 IEEE Paper 17.3