Performance Estimation and Benchmarking for Carbon Nanotube FETs and Nanodiode Arrays

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI

“…Device footprint is mainly determined by patterning tolerances, spacer width, contact, and isolation sizes. In fact, the scaled device footprint has stayed fairly constant throughout many generations from 1 μm to 65 nm technology [2]. In this paper, we postulate that even with the gate length remaining the same, selectively scaling the device footprint will provide significant circuit-level performance improvement from technology generation to technology generation.…”

Nanoelectronics: nanotubes, nanowires, molecules, and novel concepts

“…Firstly, with the aggressive scaling of Si-FETs, the gate length (source to drain separation) has come to within a factor of 2 to 3 of typical molecules under consideration. Secondly, the size of a device is typically many times larger than the conducting channel itself, with the majority of the area occupied by the contacts and device isolation structures [42]. Finally, it is not possible to reduce the electrode spacing much below 2 -3 nm due to direct tunneling between the electrodes [43].…”

“…The combination of an OR-array and an NAND-array can perform any Boolean logic through a Look-Up- The density advantage depends critically on the relative sizes of the nanodevice array, the microscale wiring, and buffer/driver device at the periphery of the nanodevice array [42,52]. Separating the logic evaluation function (nanodevice array) from the signal restoration/buffering function (microscale FETs outside the array) introduces new device/circuit design benefits.…”