This paper presents an optimization of the Sequential Spatial Adaptive Sampling (SSAS) algorithm to accelerate nearfield scanning of printed circuit boards or integrated circuits. The first originality of this approach is to configure this algorithm from the spatial distribution characteristic of near field on a planar surface. The second originality is to propose three selection criteria to adjust the targeted accuracy with the objective to reduce the measurement time. The low time-consuming algorithm selects only measurement points, which carry the most information, in order to reduce significantly the number of captured points without increasing the measurement error. The analysis of measurement results, based on this algorithm applied on two case studies, validates its effectiveness compared to the classical full regular grid sampling.
Phase-locked-loop in radiofrequency and mixed signal integrated circuit experience noise as electromagnetic interference coupled on input and power supply which translates to the timing jitter. Most of PLL noise analysis did not take into account the ageing effect. However device ageing can degrade the physical parameters of transistors and makes noise impact worse. This paper deals with the analyses of PLL immunity drift after accelerated ageing. .
This paper presents an original study about the effect of hot carrier injection stress on the DC offsets induced by electromagnetic interferences (EMI) on a nanometric NMOS transistor, which is one of the major sources of failures in analog circuits.
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