Study of the impact of hot carrier injection to immunity of MOSFET to electromagnetic interferences

Abstract

This paper presents an original study about the effect of hot carrier injection stress on the DC offsets induced by electromagnetic interferences (EMI) on a nanometric NMOS transistor, which is one of the major sources of failures in analog circuits.

Effect of Aging on Power Integrity and Conducted Emission of Digital Integrated Circuits

“…With this procedure, the characteristics of the circuit are monitored at various degrees of aging. The choice of stress conditions (stress voltage and duration) is based on a preliminary failure analysis of MOS devices developed in this technology [10] [11]. At ambient temperature, for DC stress voltages ranging from 3 to 4 V and applied between the drain and source of NMOS and PMOS devices, significant degradations of threshold voltage and carrier mobility are induced either by HCI or NBTI after several hundreds of seconds.…”

Characterization of Changes in LDO Susceptibility After Electrical Stress

“…Under ageing condition, over voltage stress is implemented on the bias current PMOS transistor (large V DS , which can accelerate degradation mechanism such as HCI). Degradation mechanism such as HCI leads to a main reduction of mobility and increase of threshold voltage [15], [19], [20] which induces the decreasing of I BIAS , the same with |g m | from (5). So the Δi D |avg is inverse to I BIAS , the Δi D |avg will increase if I BIAS decreases.…”

“…To find the origin of the immunity degradation, the best solution is prediction by modeling and simulation. In [19]- [22], the authors presented the methodology of study ageing effects based on CAD simulations and modifications of MOS device parameters extracted from measurements. The modification of MOS transistor parameters, such as threshold voltage and mobility, may affect the immunity of LDO circuit.…”

Effect of electrical stresses on digital integrated circuits power integrity

“…The choice of stress conditions (stress voltage and duration) is based on a preliminary failure analysis of MOS devices developed in this technology [9] [10]. For DC stress voltages ranging from 3 to 4 V and applied between drain and source of NMOS and PMOS devices, significant degradations of threshold voltage and carrier mobility are induced due to HCI and/or NBTI after several hundreds of seconds.…”