Ageing effect on electromagnetic susceptibility of a phase locked loop

Abstract

Phase-locked-loop in radiofrequency and mixed signal integrated circuit experience noise as electromagnetic interference coupled on input and power supply which translates to the timing jitter. Most of PLL noise analysis did not take into account the ageing effect. However device ageing can degrade the physical parameters of transistors and makes noise impact worse. This paper deals with the analyses of PLL immunity drift after accelerated ageing. .

Experimental Investigations into the Effects of Electrical Stress on Electromagnetic Emission from Integrated Circuits

“…Moreover, aging does not reduce EMC issues for integrated circuits. They can become less robust to electromagnetic interference, as shown by several recent publications [18], [19]. Similar experimental work should be carried out to clarify this question.…”

Implementation of a Low Noise Amplifier With Self-Recovery Capability

“…The chip area is 1.14 mm×0.82 mm. Accelerated aging tests at a high temperature with voltage overstress [26], [27] were carried out. The chips were stressed with the bias voltage of 1.44 V, which is 120% of the supply voltage, at the temperature of 120 • C for 400 hours.…”

Electro-magnetic robustness of integrated circuits: from statement to prediction

“…The main objective of this study is to evaluate electromagnetic drifts as function of stress types, stress conditions and stress duration. Figure 1 presents the methodology used to extract EMC level drifts induced by ageing as accurately as possible [4]. , thermal cycling or electrical overstress induce a significant variation of electromagnetic behaviour [5].…”