Abstract-In this article we propose a complete solution for the so-called Inner Receiver of an OFDM-WLAN system based on the IEEE 802.11a standard. We concentrate our investigations on three key components forming the Inner Receiver namely, the Synchronizer, the Channel Estimator and the Digital Timing Loop. The main goal is the joint optimization of the signal processing algorithms along with the implementation friendly VLSI architecture required for these three key components in order to reduce power, area and latency, without compromising the performance excessively. We provide both the mathematical details and extensive computer simulations to validate our design.

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The intercell variability of the initial state and the impact of dc and pulse forming on intercell variability as well as on intracell variability in TiN/HfO2/Ti/TiN 1 transistor – 1 resistor (1T-1R) devices in 4-kb memory arrays were investigated. Nearly 78% of devices on particular arrays were dc formed with a wordline (WL) voltage $V_{text {WL}}= 1.4$ V and a bitline (BL) voltage $V_{text {BL}}= 2.3$ V, whereas 22% of devices were not formed due to the combined effect of the extrinsic process-induced intercell variability of the initial state and the intrinsic intercell variability after dc forming. Furthermore, pulse-induced forming with pulsewidths on the order of $10~mu text{s}$ ( $V_{text {WL}}= 1.4$ V and $V_{text {BL}}= 3.5$ V) caused for 86% of devices a low-resistance state. Using a retry algorithm, we achieve 100% of formed devices. To assess and confirm the nature of the variability during forming operation and during cycling, the quantum point-contact model was considered. The modeling results demonstrate a relationship between the forming and the device performance. The cells requiring high energy for the forming operation, due to impurities in the HfO2 deposition during array processing, are those subject to poor switching performance, larger variability, and faster wear out. Devices formed by a pulse-retry algorithm show: 1) shorter endurance and 2) higher variability during cyclin

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ourth-generation wireless and mobile systems are currently the focus of research and development. They will allow new types of services to be universally available to consumers and for industrial applications. Broadband wireless networks will enable packet-based high-datarate communications suitable for video transmission and mobile Internet applications.This article is based on a project that aims to develop a single-chip wireless broadband communication system in the 5 GHz band, compliant with the Hiperlan/2 [1] and IEEE 802.11a [2] standards. Both standards specify broadband communication systems using orthogonal frequency-division multiplexing (OFDM) with data rates ranging from 6-54 Mb/s. Depending on the desired data rate, the modulation scheme adopted can be either binary phase shift keying (BPSK), quaternary PSK (QPSK), or quadrature amplitude modulation (QAM) with 1-6 b/subcarrier. The bandwidth of the transmitted signal is 20 MHz and the symbol duration is 4 µs including 0.8 µs for a guard interval.To open a broad market for consumer products, low cost of the required hardware is essential. One way to realize lowcost systems is to reduce the system complexity and implement all functions in a single chip. A single-chip solution is also advantageous in terms of performance and power dissipation when compared with multichip implementations. Fewer wires have to be routed via slow and power-hungry pad drivers. In addition, short interconnections allow faster operation of the system. Our in-house 0.25 µm SiGe:C BiCMOS technology enables the integration of complex digital baseband and data link control (DLC) functionality together with the analog RF front-end (AFE). Since the complete design flow, from system simulation down to working silicon, is on hand and under one roof, fast feedback is possible during the complete design cycle.By simultaneously considering all layers of the protocol stack, we were able to optimize the system performance. The dynamic activation/deactivation of certain blocks during transmission and reception allows us to introduce efficient power reduction mechanisms.In our vision, this broadband modem forms the communication element for a single-chip wireless engine which in turn is the heart of a complete personal digital assistant (PDA). For that purpose we also intend to integrate a TCP/IP processor and a Java-based application engine as well as advanced power management and test engines.This article is structured as follows. We give a very rough estimation of the algorithmic complexity of various blocks in the baseband and DLC layer of the wireless modem. This allows a first evaluation of the computing resources required for the modem functionality. A discussion based on these results leads to the derivation of a suitable system architecture. Some aspects of the design flow used are highlighted. A set of required hardware and software tools is listed. Some results of our work are presented. Here we focus on the implementation of specific blocks within the digital baseband processor....

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In this work a SET/RESET investigation in cycling on ReRAM arrays has been performed, in order to find the most reliable SET/RESET operation conditions. The analysis will compare DC and pulsed SET/RESET operations featuring different durations and voltages on previously DC formed 1T-1R 4kbits memory arrays. A thorough analysis of the ReRAM reliability joining the cell-to-cell variability analysis to that of cycling evaluations in complete arrays is addressed. A comparison between DC and Pulse SET/RESET in terms of switching yield, read window, device-to-device uniformity and bit error rate is reported. Finally, the impact of a temperature bake at 125C on a cycled array is shown to study the temperature impact on the array variability