Abstract-In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25-m BiCMOS technology. The core area of this chip is 6.8 mm 2 . The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption.

Abstract-In this article we propose a complete solution for the so-called Inner Receiver of an OFDM-WLAN system based on the IEEE 802.11a standard. We concentrate our investigations on three key components forming the Inner Receiver namely, the Synchronizer, the Channel Estimator and the Digital Timing Loop. The main goal is the joint optimization of the signal processing algorithms along with the implementation friendly VLSI architecture required for these three key components in order to reduce power, area and latency, without compromising the performance excessively. We provide both the mathematical details and extensive computer simulations to validate our design.

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ourth-generation wireless and mobile systems are currently the focus of research and development. They will allow new types of services to be universally available to consumers and for industrial applications. Broadband wireless networks will enable packet-based high-datarate communications suitable for video transmission and mobile Internet applications.This article is based on a project that aims to develop a single-chip wireless broadband communication system in the 5 GHz band, compliant with the Hiperlan/2 [1] and IEEE 802.11a [2] standards. Both standards specify broadband communication systems using orthogonal frequency-division multiplexing (OFDM) with data rates ranging from 6-54 Mb/s. Depending on the desired data rate, the modulation scheme adopted can be either binary phase shift keying (BPSK), quaternary PSK (QPSK), or quadrature amplitude modulation (QAM) with 1-6 b/subcarrier. The bandwidth of the transmitted signal is 20 MHz and the symbol duration is 4 µs including 0.8 µs for a guard interval.To open a broad market for consumer products, low cost of the required hardware is essential. One way to realize lowcost systems is to reduce the system complexity and implement all functions in a single chip. A single-chip solution is also advantageous in terms of performance and power dissipation when compared with multichip implementations. Fewer wires have to be routed via slow and power-hungry pad drivers. In addition, short interconnections allow faster operation of the system. Our in-house 0.25 µm SiGe:C BiCMOS technology enables the integration of complex digital baseband and data link control (DLC) functionality together with the analog RF front-end (AFE). Since the complete design flow, from system simulation down to working silicon, is on hand and under one roof, fast feedback is possible during the complete design cycle.By simultaneously considering all layers of the protocol stack, we were able to optimize the system performance. The dynamic activation/deactivation of certain blocks during transmission and reception allows us to introduce efficient power reduction mechanisms.In our vision, this broadband modem forms the communication element for a single-chip wireless engine which in turn is the heart of a complete personal digital assistant (PDA). For that purpose we also intend to integrate a TCP/IP processor and a Java-based application engine as well as advanced power management and test engines.This article is structured as follows. We give a very rough estimation of the algorithmic complexity of various blocks in the baseband and DLC layer of the wireless modem. This allows a first evaluation of the computing resources required for the modem functionality. A discussion based on these results leads to the derivation of a suitable system architecture. Some aspects of the design flow used are highlighted. A set of required hardware and software tools is listed. Some results of our work are presented. Here we focus on the implementation of specific blocks within the digital baseband processor....

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A method is presented to simultaneously investigate in situ the relaxation and diffusion behavior of Sir-,Ge, layers on silicon substrates using a conventional x-ray powder diffractometer with a high-temperature attachment. The method allows the direct determination of the time and temperature dependence of the relaxation and of the maximum Ge content. The diffusivity of Ge in silicon was studied by x-ray diffraction and secondary ion mass spectroscopy measurements. A nonlinear dependence of the effective diffusion coefficient on the Ge content was deduced by solving a diffusion equation.

In this paper, we propose a CoOrdinate Rotation DIgital Computer (CORDIC) like processor for computing absolute magnitude of a vector and its corresponding phase angle. It does not require the scale factor compensation step and addition/subtraction operation along the z datapath, has a convergence range over the entire coordinate space and shows similar error characteristics as that of the conventional CORDIC. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications.

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