System design considerations for a PSSS transceiver for 100Gbps wireless communication with emphasis on mixed signal implementation

Javed, Abdul Rehman; Scheytt, J. Christoph; KrishneGowda, Karthik; Kraemer, Rolf

doi:10.1109/wamicon.2015.7120419

Cited by 30 publications

(18 citation statements)

References 6 publications

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“…4). Thus, the sampling clock is reduced by N -times, where the N is the spreading sequence length (N = 15, according to the work published in [8], [23], [27]). These two advantages of the PSSS allow us to cross the 100 Gbps data rate barrier on the baseband level.…”

Section: E Parallel Sequence Spread Spectrum (Psss)mentioning

confidence: 99%

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

et al. 2019

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In this paper, we show our 165 Gbps data link layer processor for wireless communication in the terahertz band. The design utilizes interleaved Reed-Solomon codes with dedicated link adaptation, fragmentation, aggregation, and hybrid-automatic-repeat-request. The main advantage is the low-chip area required to fabricate the processor, which is at least two times lower than the area of low-density paritycheck decoders. Surprisingly, our solution loses only ∼1 dB gain when compared to high-speed low-density parity-check decoders. Moreover, with only 2.38 pJ/bit of energy consumption at 0.8 V, one of the best results in the class of comparable implementations has been achieved. Alongside, we show our vision of a complete 100 Gbps wireless transceiver, including radio frequency frontend and baseband processing. For the baseband realization, we propose a parallel sequence spread spectrum and channel combining at the baseband level. Challenges to high-speed wireless transmission at the terahertz band are addressed as well. To the authors' best knowledge, it is one of the first data link layer implementations that deal with a data rate of ≥ 100 Gbps. INDEX TERMS 100 Gbps wireless, terahertz communication, Reed-Solomon coding, data link layer. The associate editor coordinating the review of this manuscript and approving it for publication was Khursheed Aurangzeb. FIGURE 1. Discussed wireless radio-transceiver system. and baseband implementations. Fig. 1 depicts the architecture of the discussed wireless radio-transceiver. A. CHALLENGES TO HIGH-SPEED WIRELESS COMMUNICATIONS Ultra-high speed wireless systems require either very high bandwidth or very high bandwidth efficiency. In cellular architectures like LTE or 5G high bandwidth efficiency is in the focus. This is due to the limited bandwidth in the available radio bands. Increasing the bandwidth efficiency requires a corresponding increase in signal processing power

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Section: E Parallel Sequence Spread Spectrum (Psss)mentioning

confidence: 99%

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

et al. 2019

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“…1, it is possible to provide channels exceeding 50 GHz of continuous bandwidth, which allow for very high data rates, assuming uncomplicated modulation schemes [1]- [3]. One of the novel modulation techniques that could be considered for such wide radio frequency (RF) channels is the so-called Parallel Sequence Spread Spectrum (PSSS) [4]- [6], which considerably simplifies transmitter and receiver baseband design due to its inherent parallelism and analog-friendly architecture [7]. The main advantage of PSSS is a lightweight baseband implementation that allows to sample and process the baseband signal in parallel ADC structures and baseband threads (Fig.…”

Section: Introductionmentioning

confidence: 99%

“…The main advantage of PSSS is a lightweight baseband implementation that allows to sample and process the baseband signal in parallel ADC structures and baseband threads (Fig. 2) [7]. This feature is especially important for future high-speed wireless channels located in the THz band, where the ADCs and DACs need to process large bandwidth.…”

Section: Introductionmentioning

confidence: 99%

“…Due to removed sidelobes, the improved PSSS scheme shows excellent BER performance and approaches QPSK and QAM modulations in AWGN. To the best of our knowledge, such a method has never been employed for generating PSSS sequences [5]- [7], [16]- [19]. Our algorithm has five main advantages when compared to the state of the art PSSS schemes:…”

Section: Introductionmentioning

confidence: 99%

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Real-Valued Spreading Sequences for PSSS Based High-Speed Wireless Systems

et al. 2022

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In past years, Parallel Sequence Spread Spectrum (PSSS) has attracted significant attention as a modulation technique for wireless communication systems targeting data rates of 100 Gb/s and beyond. PSSS allows designing high-speed baseband processors, which can be partially implemented in the analog domain. It uses multiple analog-to-digital converters (ADCs) to sample the received baseband signal in parallel, significantly relaxing the sampling rate and ADC complexity. However, due to the sidelobe effects of bipolar m-sequences, PSSS shows lower performance than standard digital modulation schemes. This paper proposes real-valued PSSS spreading sequences with attenuated autocorrelation sidelobes. Such sequences show excellent bit error rate (BER) performance. Moreover, our sequences do not have length restrictions of 2 m -1, like in the case of m-sequences, and reduce the chip area required to implement PSSS transceiver. The proposed sequences also reduce the peak-to-average power ratio (PAPR) of PSSS.INDEX TERMS PSSS, high-speed wireless communications, baseband, genetic algorithm, spreading sequences, sidelobe mitigation. FIGURE 1. Average millimeter-and THz-wave atmospheric absorption. Figure retrieved from [1].

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“…The baseband and PHY layer are investigated under Real100G.COM activity [3]. More information on the dedicated PHY layer and baseband processing can be found in [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Data Link Layer Considerations for Future 100 Gbps Terahertz Band Transceivers

Lopacinski

Brzozowski

Kraemer

2017

Wireless Communications and Mobile Computing

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This paper presents a hardware processor for 100 Gbps wireless data link layer. A serial Reed-Solomon decoder requires a clock of 12.5 GHz to fulfill timings constraints of the transmission. Receiving a single Ethernet frame on a 100 Gbps physical layer may be faster than accessing DDR3 memory. Processing so fast streams on a state-of-the-art FPGA (field programmable gate arrays) requires a dedicated approach. Thus, the paper presents lightweight RS FEC engine, frames fragmentation, aggregation, and a protocol with selective fragment retransmission. The implemented FPGA demonstrator achieves nearly 120 Gbps and accepts bit error rate (BER) up to 2e-3. Moreover, redundancy added to the frames is adopted according to the channel BER by a dedicated link adaptation algorithm. At the end, ASIC synthesis results are presented including detailed statistics of consumed energy per bit.

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System design considerations for a PSSS transceiver for 100Gbps wireless communication with emphasis on mixed signal implementation

Cited by 30 publications

References 6 publications

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

Data Link Layer Processor for 100 Gbps Terahertz Wireless Communications in 28 nm CMOS Technology

Real-Valued Spreading Sequences for PSSS Based High-Speed Wireless Systems

Data Link Layer Considerations for Future 100 Gbps Terahertz Band Transceivers

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