No abstract

Abstract-The paper presents an evolutionary approach to the design of fault-tolerant VLSI (very large scale integrated) circuits using EHW (evolvable hardware). The EHW research area comprises a set of applications where GA (genetic algorithm) are used for the automatic synthesis and adaptation of electronic circuits. EHW is particularly suitable for applications requiring changes in task requirements and in the environment or faults, through its ability to reconfigure the hardware structure dynamically and autonomously. This capacity for adaptation is achieved via the use of GA search techniques. In our experiments, a fine-grained CMOS (complementary metal-oxide silicon) FPTA (field-programmable transistor array) architecture is used to synthesize electronic circuits. The FPTA is a reconfigurable architecture, programmable at the transistor level and specifically designed for EHW applications.The paper demonstrates the power of EA to design analog and digital fault-tolerant circuit. It compares two methods to achieve fault-tolerant design, one based on fitness definition and the other based on population.The fitness approach defines, explicitly, the faults that the component can encounter during its life, and evaluates the average behavior of the individuals. The population approach, on the other hand, uses the implicit information of the population statistics accumulated by the GA over many generations.The paper presents experiment results obtained using both approaches for the synthesis of a fault-tolerant digital circuit (XNOR) and a fault-tolerant analog circuit (multiplier). The experiments show that the EA (evolutionary algorithm) can synthesize fault-tolerant designs for both the analog and digital functions circuits that can recover for functionality when lost due to a-priori unknown faults by finding new circuit configurations that circumvent the faults.The paper shows that although the classic fault-tolerant design approach is able to create a reliable circuit design by evaluating the behavior of the circuit when well known faults are injected during the evolutionary process, better circuit performance, in less computation time, for a same fault-tolerant degree is achieved by allowing the evolutionary design process to be free of all faults constraints.

No abstract

We present in this work the application of a set of different evolutionary methodologies in the problem of electronic filter design. The main objectives are to find out which constraints in the filter topologies, if any, must be observed aEong the evolutionary process and t o study the problem of convergence t o parsimonious circuits. The new area of Evolutionary Electronics is introduced, an evolutionary methodology based on variable length representation is presented and the results on the evolution of low-pass and band-pass filters are described.

No abstract

Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how highperformance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mm CMOS technology and silicon tests showed good correspondence with the simulations.

No abstract

No abstract