A b s t r a c t Results of new CMOS-integrated PIN photodiodes in optoelectronic integrated circuits (OEICs) for applications in optical storage systems, in optical data transmission and in optical interconnects are presented. The rise and fall times of the integrated PIN photodiodes are below 0.3 ns. The CMOS-integrated PIN photodiodes are sufficient for a NRZ data rate of 1.5 Gb/s and the results show that PIN CMOS receiver OEICs in submicron technologies enable data rates up to 1 Gb/s. These photodiodes combine this high speed with a high quantum efficiency of approximately 50 %. The further improvement of their quantum efficiency above 90 % by the integration of an antireflection coating is discussed. Low-offset PIN-CMOS-OEICs for the application in digital-versatile-disk systems with bandwidths in excess of 32 MHz are presented. A highspeed PIN-CMOS-OEIC in 1.0 pm technology for optical data transmission exhibits a data rate of 622Mb/s.
Three-dimensional integration techniques offer not only a method for increasing the packing density, but also most promising opportunities for the realization of multifunctional circuits: mixed circuit technologies, (e.g. digital I analog), mixed process technologies, (e.g. CMOS I bipolar), and the combination of different semiconductor materials. Fig. 1.
As one of the steps towards this aim we developed a 2 pm 3D-CMOS process which allows the fabrication of MOS devices in two layers. We realized NMOS devices in the silicon substrate and CMOS devices, as inverters and ring oscillators, in a 0.5 lun-thick recrystallized polysilicon layer. A schematic cross-section of a fabricated 3D-device is shown inThe as-deposited polysilicon upper device layer is recrystallized by means of an argon laser system. Care has to be exercized to prevent substrate damage. We investigated the influence of different recrystallization parameters on substrate damage, detected by Wright etching of bevelled samples and x-ray topograms. On the basis of these investigations we obtain a high quality SO1 layer without generating any crystal damage in the underlying silicon. This is also confirmed by the electrical characteristics of fabricated MOS devices, which do not show any degradation as compared with customary bulk devices. Typical results are shown in Figs. 2 and 3. An undesired effect is the occurrence of mass transport upon recrystallization of the silicon film. With the standard film thickness of 0.5 pm this is no problem, but it is known that thin film SO1 MOS transistors (thickness about 0.1 pm) exhibit remarkably improved properties. Therefore we are working on measures to minimize mass transport in order to allow the thinning of recrystallized silicon layers and to fabricate thin film SO1 devices. 72
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