Three dimensional metallization for vertically integrated circuits

Bollmann, D.; Braun, R.; Buchner, R.; Cao-Minh, U.; Engelhardt, M.; Errmann, G.; Grassl, T.; Hieber, K.; Hübner, H.; Kawala, G.; Kleiner, M.B.; Klumpp, Armin; Kühn, Stefan; Landesberger, Christof; Lezec, Henri J.; Muth, W.; Pamler, W.; Popp, R.; Renner, Elisabeth; Ruhl, G.; Sanger, Amit; Scheler, Ulrich; Schmidt, C.; Schwarzl, S.; Weber, Josef; Weber, W.; Ramm, Peter

doi:10.1016/s0167-9317(97)00092-0

Cited by 84 publications

(25 citation statements)

References 4 publications

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“…Low-temperature (< 450 0C) copper-copper or polyemide based wafer bonding can be used to bond two fully processed wafers for fabricating 3-D ICs [45,46,47]. In 3-D IC technology based on wafer bonding, after the fabrication of individual wafer, top wafer is attached to a handle wafer, and it is thinned down from the back side.…”

Section: O1mentioning

confidence: 99%

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System-level performance evaluation of three-dimensional integrated circuits

Rahman¹,

Reif²

2000

IEEE Trans. VLSI Syst.

174

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As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies.Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3 rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% -50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.

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Section: O1mentioning

confidence: 99%

“…back-to-front bonding); after the bonding process, the handle wafer is released. Through wafer vias for inter-device layer connections can be formed before or after the bonding step [46,47]. Ideally, the processing steps required to bond two wafers can be repeated to bond as many wafers as desired.…”

Section: O1mentioning

confidence: 99%

System-level performance evaluation of three-dimensional integrated circuits

Rahman¹,

Reif²

2000

IEEE Trans. VLSI Syst.

174

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“…Ramm et al [17] presented the so-called interchip via concept, which is based on dry etched cavities by reactive ion etching (RIE). These cavities are as deep as 14 lm and have an aspect ratio of 5-10.…”

Section: Single Feedthroughsmentioning

confidence: 99%

“…Spin-on glass n/a n/a Feasibility study [60] W (CVD) TEOS SiO 2 2-4 X n/a CMOS wafer stacks [17] Polysilicon (LPCVD) Thermal SiO 2 n/a n/a 3D micro vision system [61] Al (sputtering) Thermal SiO 2 n/a n/a Integrated sensors [18] Multiple feedthroughs -wet etched holes Al (evaporation) LPCVD Si 3 N 4 < 5 X < 1 Electrical feedthroughs [20] Ti-Au (evaporation)…”

Section: Stacking Approach For An Integrated Microphonementioning

confidence: 99%

Multiple Through-wafer Interconnects for MEMS Applications

Heschel

Kuhmann²,

Bouwstra³

2001

Sensors Update

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This chapter reports on the design and manufacturing of multiple through-wafer interconnects for stacking of microelectromechanical devices. The feedthroughs have been applied to an interconnect (intermediate) layer for an integrated microphone. The integrated microphone consists of the transducer part and an application specific integrated circuit (ASIC). The two parts are joined by stacking them on top of each other with the interconnect (intermediate) layer between them. The intermediate layer is a multifunctional layer. It provides the microphone with an acoustic frontchamber. The intermediate layer ensures the interchange of acoustical and electrical signals with the environment. Also, the intermediate layer protects the microphone during dicing, chip handling and in operation. The two active components are electrically connected through the intermediate layer by multiple wafer frontside to backside interconnects. The feedthrough interconnects are provided with under bump metallizations (UBM), solder bumps and sealing rings on the microphone side and top surface metallizations (TSM) on the ASIC side. The entire metallization system is based on electroplating techniques. The patterning of the metallizations has been done utilizing an electrodepositable photoresist (EDPR) as a plating mold. Several EDPR processes have been developed which are optimized for the respective metallization. The feedthrough interconnects have been optimized in terms of series resistance and parallel capacitance. Electrical characterization of the feedthrough interconnects has been carried out analytically and experimentally. The series resistance of one single interconnect wire is in the order of 100 mX. The parallel (parasitic) capacitance is in the order of 2 pF. Coupling between two adjacent feedthrough interconnects is negligible for low relative humidity (<50%). For high relative humidity (>90%) the impedance between two wires may be reduced due to a condensed water film. Sensitivity measurements performed before and after bonding of the interconnect layer to the microphone showed identical results which proves sufficient (TX) isolation between the feedthrough wires.

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“…There are several proposed applications for three-dimensional ICs [5,6,7,8,9,10,11] and much research effort has been carried out on the new technologies for vertically integrated circuits. Beside the stacking of Multi-Chip-Modules (MCMs) [12], there exist several basic approaches to vertically connect multiple silicon layers [13,14,15,16,17].…”

Section: Introductionmentioning

confidence: 99%