Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.

This paper presents a theoretical and experimental study of the recrystallization behavior of polycrystalline silicon films amorphized by self-implantation. The crystallization behavior was found to be similar to the crystallization behavior of films deposited in the amorphous state, as reported in the literature; however, a transient time was observed, during which negligible crystallization occurs. The films were prepared by low-pressure chemical vapor deposition onto thermally oxidized silicon wafers and amorphized by implantation of silicon ions. The transient time, nucleation rate, and characteristic crystallization time were determined from the crystalline fraction and density of grains in partially recrystallized samples for anneal temperatures from 580 to 640 °C. The growth velocity was calculated from the nucleation rate and crystallization time and is lower than values in the literature for films deposited in the amorphous state. The final grain size, as calculated from the crystallization parameters, is 2.5 μm for an anneal temperature of 580 °C and 1.5 μm for an anneal temperature of 640 °C and is in agreement with transmission electron microscopy dark-field images of completely recrystallized samples that show grain sizes of approximately 1–2 μm.

Silicon wafers, coated with 300 nm evaporated copper, were successfully bonded at 450°C for 30 min with a postbonding anneal in N 2 for 30 min. The postbonding anneal was required for successful bonding, but the annealing temperature did not influence the bond strength from 400 to 620°C. The inclusion of a tantalum diffusion barrier for Cu did not affect the bonding strength or the bonding temperature.Copper metallization, with low electrical resistivity and high electromigration resistance, 1 is rapidly developing into the mainstream interconnect technology. Along with advances in low k dielectrics, these are two practical approaches in reducing interconnect RC delay in integrated circuits. However, new schemes, such as direct three-dimensional integration, have shown promises in significant reduction of interconnect delay and an increase in system performance. 2,3 In exploring the implementation of 3-D integrated circuits, wafer bonding is an attractive technology option.In direct 3-D integration, active device wafers are bonded together, while all active layers are electrically interconnected using high aspect ratio vias. The bonded device wafers are assumed to contain multiple aluminum metal layers and interlevel dielectrics (ILD), thus requiring low-temperature bonding below 450°C to avoid Al degradation. 4 Referring to Fig. 1, one implementation of 3-D integration is to use polymer adhesives, such as polyimide or epoxy, to bond wafers at low curing temperatures ranging from 150 to 400°C. [5][6][7] Interwafer vias are then etched through the ILD, the thinned top Si wafer, and the cured polymer layer, with an approximate depth of 20 µm. 7 Furthermore, via filling is made using oxide spacers for insulation, chemical vapor deposited (CVD) TiN for the metal liner, and CVD W for plug formation.Instead of polymers, one can also use borophosphosilicate glass (BPSG) as the bonding adhesive. 8 However, when using low melting point glasses (450°C or more) for wafer bonding, global planarity of the glass film is needed for good contact between the wafers and to eliminate void formation. Thus, chemical mechanical polishing (CMP) or reflow of the glass is necessary prior to bonding. For both planarization methods, process variations are difficult to control. To alleviate processing issues such as film planarity or complex deeptrench etching procedures, a metal thermocompression bonding method has been proposed. Thin metal films from both wafers will fuse together upon applying compressive force and heat, which provide enough adhesion to bond the wafers together. 9 Figure 2 shows metal (Cu) bumps on both wafers that can serve as electrical contacts between via on the top wafer and Al interconnects on the bottom wafer. These metal bumps also function as small bond pads for wafer bonding. At the same time, dummy metal patterns can be made to increase the surface area for wafer bonding. They can also act as auxiliary structures such as ground planes or heat conduits for the Si active layers. This paper reports on Cu/Ta wafer...

As the critical dimensions in VLSI design continue to shrink, system performance of integrated circuits (ICs) will be increasingly dominated by interconnect delay [1]. For the technology generations approaching 50 nm and beyond, innovative system architectures and interconnect technologies will be required to meet the projected system performance [2]. Interconnect material solutions such as copper and low-k inter-level dielectric (ILD) offer only a limited improvement in system performance. Significant and scalable solutions to the interconnect delay problem will require fundamental changes in system design, architecture, and fabrication technologies.Three-dimensional (3-D) ICs can alleviate interconnect delay problems by offering flexibility in system design, placement and routing. They (3-D ICs) can be formed by vertical integration of multiple device layers using wafer bonding, recrystallization, or selective epitaxial growth. The flexibility to place devices along the vertical dimension allows higher device density and smaller form factor in 3-D ICs. The critical signal path that may limit system performance can also be shortened to achieve faster clock speed. By 3-D integration, device layers fabricated with different front-end process technologies can be stacked along the 3 rd dimension to form systems-on-a-chip [3]. In this thesis work, opportunities and challenges for 3-D integration of logic networks, microprocessors, and programmable logic have been explored based on system-level modeling and analysis. A stochastic wire-length distribution model has been derived to predict interconnection complexity in 3-D ICs. As more device layers are integrated, the 3-D wire-length distribution becomes narrower compared to that of 2-D ICs, resulting in a significant reduction in the number and length of semi-global and global wires. In 3-D ICs with 2-4 device layers, 30% -50% reduction in wire-length can be achieved. Besides performance modeling, thermal analysis has also been performed to assess power dissipation and heat removal issues in 3-D ICs. The total capacitance associated with signal interconnects and clock networks can be reduced by 3-D integration, leading to lower power dissipation for system performance comparable to that of 2-D ICs. However, for higher system performance in 3-D ICs, power dissipation increases significantly, and it is likely that innovative cooling techniques will be needed for reliable operation of devices and interconnects.

The morphology and bond strength of copper-bonded wafer pairs prepared under different bonding/annealing temperatures and durations are presented. The interfacial morphology was examined by transmission electron microscopy while the bond strength was examined from a diesaw test. Physical mechanisms explaining the different roles of postbonding anneals at temperatures above and below 300°C are discussed. A map summarizing these results provides a useful reference on process conditions suitable for actual microelectronics fabrication and three-dimensional integrated circuits based on Cu wafer bonding.

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A review is presented of the self-implantation method which has been developed to achieve high-quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin-film transistors (TFTs). In this method, silicon ions are implanted into an as-deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with 〈110〉 orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550–700 °C. With optimized process conditions, average grain sizes of 1 μm or greater can be obtained. First, an overview is given of the thin-film transistor technology which has been the greatest motivation for the research and development of the self-implantation method. Then the mechanism of selective amorphization by the silicon self-implantation and the crystallization by thermal annealing is discussed. An analytical model and experimental results are described. Polycrystalline silicon TFTs fabricated using the self-implanted polycrystalline silicon thin-films are then reviewed. The high-quality polycrystalline silicon thin films processed with the self-implantation method results in excellent TFT characteristics for both n- and p-channel devices thereby allowing complementary metal-oxide-semiconductor integrated circuits. High mobilities of around 150 cm2/V s for n-channel TFTs and around 50 cm2/V s for p-channel TFTs as well as on-to-off current ratios of 1×108 have been achieved. Fabrication and characterization of polycrystalline silicon TFTs with channel dimensions comparable to or smaller than the grain size of polycrystalline silicon films are also described to present a case study to discuss the self-implantation process and associated technologies. Finally, new approaches that extend the self-implantation method to control grain-boundary locations are discussed. If grain-boundary locations can indeed be controlled, the self-implantation method will become even more valuable in developing future high-performance TFT integrated circuits.

A system and a procedure using chemical vapor deposition of silane at very low pressures (<10−2 Torr) have been developed for depositing uniform, specular silicon epitaxial films both with and without plasma enhancement at temperatures as low as 650 °C. In situ cleaning of the substrate surface that overlaps into the deposition is the most critical aspect of the procedure. Undoped films deposited on substrates heavily doped with antimony or boron have abrupt doping profiles. Preliminary measurements indicate that the hole mobility of epitaxial films obtained with this process is 90% of that in bulk silicon. Films oxidized and decorated with a Secco etch show twice as many defects as a similarly treated substrate. Nonplasma growth kinetics are sensitive to surface conditions such as crystallographic orientation, and surface diffusion of adsorbed species appears to be the rate-limiting step for depositing epitaxial films above 700 °C. Around 650 °C, the growth mechanism appears to change, possibly due to the increased presence of hydrogen on the surface. Finally, plasma enhances the growth rate, and plasma kinetics do not seem to be sensitive to surface conditions.