More and more cores are integrated onto a single chip to improve the performance and reduce the power consumption of CPU without the increased frequency. The cores are connected by lines and organized as a network, which is called network on chip (NOC) as the promising paradigm of the processor design. However, it is still a challenge to enhance performance with lower power consumption. The core issue is how to schedule the tasks to the different cores to take full advantages of the on-chip network. In this paper, we proposed a novel scheduling algorithm with power-aware optimization for NOC. The traffic of the tasks will be analyzed. The tasks of the same program with high communication with the others will be mapped to the on-chip network as neighborhoods. And then the tasks of different programs are mapped to the cores step by step. The mapping of the tasks and the cores is computed at run-time dynamically and implement the online scheduling. The experimental results showed that this proposed algorithm can reduce the power consumption in communication with the performance enhanced.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.