Distributed Memory Management Units Architecture for NoC-based CMPs

Cao, Man; Xie, Bin; Fuming, Qiao; Shi, Qingsong; Chen, Tianzhou; Yan, Like

doi:10.1109/cit.2010.53

Cited by 5 publications

(4 citation statements)

References 12 publications

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“…Our approach in this paper is similar to the previous works that separate MMUs from the processors and deploy them in NoC [23]- [25]. However, compared to the previous works aimed at MPSoC for high-performance platforms and to improve the performance of MPSoC, this approach aims at a lightweight platform in which the MMUs embedded in the NoC should be light and to simply support the address translation.…”

Section: A Proposed Approachmentioning

confidence: 99%

“…For example, an on-chip centralized hardware MMU module was presented for data allocation on the distributed shared memory space in the NoC-based MPSoC [22]. And, a distributed MMU architecture exploiting the NoC architecture was introduced to reduce the memory access bottleneck in contrast of traditional MMU [23]. This work targets the mesh-based NoC and provides detailed memory access mechanism that effectively improves network throughput.…”

Section: A Proposed Approachmentioning

confidence: 99%

“…Especially, we paid attention to the network-on-chip (NoC) that is a common IP for system interconnect in modern embedded system platforms [8], [27], [28]. Then, attention has been paid to previous researches on the placement of MMUs in network-on-chip (NoC) [23]- [25]. Starting with a distributed MMU that uses multiple MMUs as the resources of NoC to perform operations to handle memory access requests, we propose a new NoC design that includes a lightweight MMU architecture suitable for lightweight embedded systems.…”

Section: Introductionmentioning

confidence: 99%

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MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems

et al. 2019

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With the advent of the Internet-of-Things (IoT) era, the demand for lightweight embedded systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading the development of lightweight embedded systems. However, as the IoT era gets more sophisticated, existing ULP processors are expected to reach a critical limit in the absence of a memory management unit (MMU) in that multiple programs cannot be run in the MMU-less embedded systems. To tackle this issue, we propose an architecture in which the MMU is embedded in a network-on-chip (NoC). Through the proposed approach, NoC offers MMU functionality without modifying the processor design, allowing developers to easily leverage the existing ULP lightweight processors and build embedded systems that support multiprocessing. In this paper, along with the details of the proposed MMU-embedded NoC (MMNoC) design, a prototype platform including the MMNoC and dual RISC-V processors is provided. The prototype platform is synthesized with FPGA and Samsung 28 nm FD-SOI technology to verify the functional accuracy and small performance, area, and power overhead of the MMNoC. INDEX TERMS Network-on-chip, NoC, memory management unit, MMU, embedded system.

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Section: A Proposed Approachmentioning

confidence: 99%

Section: A Proposed Approachmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems

et al. 2019

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“…Man et. al [6] discuss the problem of limited bandwidth when using a unique, centralized Memory Management Unit (MMU). As the number of PEs increases, the number of memory references also tends to increase, therefore the sequential structure of a centralized MMU can become the bottleneck of the system.…”

Section: Introductionmentioning

confidence: 99%

Distributed Shared Mamory for NoC-based MPSoCs

Chaves¹,

Moraes²

2020

JICS

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As the number of cores and functionalities integrated in embedded devices increases, the amount of memory used on these devices also increases, justifying the development of memory architectures that present scalability, low energy consumption and low latency. Two factors impact the scalability of MPSoC systems: cache access latency and energy consumption. The distance of the processors to the cache banks and the cache coherence protocol influences both factors. This work proposes a physically distributed data L2 cache as the cache architecture for a NoC-based MPSoC, because it allows the concept of clustering, and the implementation of data migration algorithms to reducing cache access latency. Results show that the number of cycles required to execute a given application might reduce 23% with the appropriate number of L2 cache banks. Also, a directory-based cache coherence protocol was implemented, exploiting the NoC physical services to improve performance. Results show a reduction of 17% in the number of clock cycles and a reduction up to 86% (average reduction: 39%) in energy consumption for some cache transactions.

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