FPGA based hardware-software co-designed dynamic binary translation system

A Hardware-assisted Translation Cache for Dynamic Binary Translation in Embedded Systems

“…Despite the work presenting substantial improvements over software-only deployments, it proposes the integration of hardware extensions at architectural level into an intellectual property (IP) Arm core processor. Following Baiocchi, Yao et al [4] also integrate SPM in FPGA to reduce context switching overheads. Furthermore, they present a hardware deployment of the mechanism proposed in [10], as a simple look-up-table (LUT) composed by a contentaddressable memory (CAM) and a RAM.…”

“…On an effort to speed up the translated code management (i.e., to add and search translation entries) and obtaining a scalable cache management method, the TCache management effort is delegated to hardware through an FPGA-based solution. The approach followed by [4] is well suited to be applied because it is non-intrusive and takes full benefit of available hardware, but it still relies on a heavy software-based backup mechanism to handle missing translations from the hardware management. The software hash table mechanism should be avoided in the resource-constrained embedded systems, because of the well known latency it originates.…”

“…A modified approach of [4] was followed, however the usage of software hash tables was avoided. The TBB caching, the eviction policy and the available space management are processed using a software approach, while adding new TBB entries and searching for a TBB are processed by auxiliary hardware.…”

“…The hardware implementation is based on the regular TCache memory space allocated on the target data memory plus a LUT, similar to a fully associative cache (CAM + RAM) on a integrated implementation, as depicted in Figure 2. In this approach, and diverting from the one presented in [4], the output of the CAM is not returned to the microprocessor. In case of a source address hit, the target address is directly forwarded to the microprocessor.…”

“…Among other suggestions, the authors point that research in overhead reduction through hardware support should be conducted in order to achieve near zero overhead DBT. Yao et al identified that common DBT systems suffer performance loss because of architectural heterogeneity among ISAs, control flow and context switches [4]. In the same work, it is proposed an field-programmable gate array (FPGA)-based hardware/software co-designed acceleration solution, achieved through register replication in reconfigurable hardware and ISA extensions.…”