Dynamic Compilation Framework with DVS for Reducing Energy Consumption in Embedded Processors

Shi, Qingsong; Chen, Tianzhou; Xiao, Liang; Huang, Jiangwei

doi:10.1109/icess.2008.47

Cited by 5 publications

(3 citation statements)

References 10 publications

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“…Approaches include using a mapping algorithm to run different components of an application on different chip cores while independently varying their voltages [6], using dynamic compilers with dynamic voltage scaling (DVS) techniques [7], using compiler-directed DVS for reducing network-on-chip energy [8], or proposing a petri net based model for setting frequencies in multiple clock domain micro-architectures [9].…”

Section: Motivation and Previous Workmentioning

confidence: 99%

Optimising Energy Consumption of Design Patterns

Noureddine

Rajan

2015

2015 IEEE/ACM 37th IEEE International Conference on Software Engineering

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Abstract-Software design patterns are widely used in software engineering to enhance productivity and maintainability. However, recent empirical studies revealed the high energy overhead in these patterns. Our vision is to automatically detect and transform design patterns during compilation for better energy efficiency without impacting existing coding practices. In this paper, we propose compiler transformations for two design patterns, Observer and Decorator, and perform an initial evaluation of their energy efficiency.

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Section: Motivation and Previous Workmentioning

confidence: 99%

Optimising Energy Consumption of Design Patterns

Noureddine

Rajan

2015

2015 IEEE/ACM 37th IEEE International Conference on Software Engineering

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“…They implement two different scheduling algorithm based on a directed acyclic graph (DAG) using voltage scaling. Shi et al [37] present a framework for embedded processors using a dynamic compiler. Their compiler-based approach specifically utilizes the OS-level information and hardware status.…”

Section: Related Workmentioning

confidence: 99%

Compiler-Directed Energy Reduction Using Dynamic Voltage Scaling and Voltage Islands for Embedded Systems

Öztürk

Kandemir

Chen

2013

IEEE Trans. Comput.

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“…Recent studies use Dynamic Power Management for improving energy consumption. One of the approach is varying voltage independently using dynamic compilers with dynamic voltage scaling (DVS) techniques [9] [10]. Dynamic Voltage and Frequency Scaling (DVFS) is another approach where both voltage and frequency are varied as required [11] [12].…”

Section: Related Workmentioning

confidence: 99%

Power Optimization of CFD Applications on Heterogeneous Architectures

Ahmed¹,

Khan²,

Ahmed³

et al. 2017

IJCA

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Computational fluid dynamics (CFD) is widely used by the scientific computing community to solve various fluid flow problems. High performance computing (HPC) enable faster CFD simulations with higher solution accuracies. Many CFD applications are run on multicore and multiprocessor platforms and are being increasingly ported to run on computational accelerators such as graphical processing units (GPUs) to increase the performance. The increase of computational power is necessary to allow faster computing, which in turn increases the power consumption. The issue of the power consumption has to be addressed, particularly in applications such as CFD, where the simulations may need to be executed iteratively for a large number of times, each iteration taking a large amount of time, in order to obtain appropriately accurate results. Poweraware computing is concerned with devising energy efficient methods. Techniques such as Dynamic voltage and frequency scaling (DVFS) and offlining can be used to reduce power consumption and increase the energy efficiency of applications. In this paper, we present a combination of these techniques and apply to CFD applications running on heterogeneous architectures. We reduce the overall power consumption with a small performance loss. Precisely, for DVFS, we save 4% to 23.5% of energy with a performance loss of 0.6% to 9.8%. Similarly, for online-offline mode, we save 22% of energy with a performance loss of 0.3%.

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Dynamic Compilation Framework with DVS for Reducing Energy Consumption in Embedded Processors

Cited by 5 publications

References 10 publications

Optimising Energy Consumption of Design Patterns

Optimising Energy Consumption of Design Patterns

Compiler-Directed Energy Reduction Using Dynamic Voltage Scaling and Voltage Islands for Embedded Systems

Power Optimization of CFD Applications on Heterogeneous Architectures

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