This paper presents a low-power, high-precision capacitance-to-voltage converter (CVC) for grounded capacitive sensors. To measure very small capacitance variations in the presence of a large offset capacitance, a new zoom-in structure is proposed. The major non-idealities of the CVC such as the settling error, charge injection, and parasitic capacitance of the switches are minimized through an optimized design. Accordingly, it is shown that the zoom-in technique can significantly reduce many of these errors. The effect of the parasitic capacitances around the sensor capacitance is significantly reduced by using a switched-capacitor-based active-shielding technique. The interface is designed as an integrated circuit using a standard 0.18-μm CMOS technology. Simulation results show that for a sensor capacitor with a nominal value of 10 pF, variation of only 200 fF, and parasitic capacitance of up to 20 pF, a worst-case capacitance error of 0.2 fF can be achieved by taking into account the layout mismatches and the interconnection effects. The achieved latency is 100 μs, and the CVC consumes only 80 μA from a 2-V power supply. The simulated input capacitance resolution for this latency is 123 aF, which is quite close to our calculated resolution (126 aF). This resolution corresponds to an energy efficiency of 9.82 pJ/Step. A temperature sweep simulation has been performed over the temperature range from −45°C to 125°C to demonstrate the small thermal drift of the designed circuit.

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This work offers the use of an active inductor and capacitor to build RF band-pass filter with 0.18μm and TSMC process. Based on the proposed structure, a prototype 1 GHz active filter designed and simulated in a 0.18μm CMOS technology. Simulation results for the designed RF band-pass filter show S21 > 19dB and consuming power less than 14 mW from 1.8 V supply voltage. The absolute values of reflection parameters (|S11| and |S22|) are about 60 dB. Low-bandwidth linear noise at output node are less than -170 dB and Advanced Design System (ADS) used to produce 1 GHz band-pass active filter simulation results.

This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M + k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between two consecutive integer numbers. Operating in 2.5 GHz, total circuit including digital part consumes 15.5 mW from 1.8 V supply voltage. At the proposed architecture, reference clock is injected into a ring oscillator in specified times and to the specified delay-stages to synthesize the fractional frequency multiplication as well as resetting the accumulated jitter during previous cycles. Operating in maximum speed, simulated RMS (root-mean-square) and PTP (peak-to-peak) jitter values are 1.8 and 14.5 ps, respectively, while the settling time is 5 us.

A circuit with a low-power low-noise amplifier and a Gm-C ultra-low-power filter is proposed in this paper for portable electroencephalogram (EEG) acquisition applications. The proposed circuit contains a two-stage chopper-stabilized fully recycling folded cascode (TSRFC) amplifier and a second-order continuous-time Gm-C low pass filter (LPF) with ultra-low-power consumption. The noise and input offset are reduced using the chopper-stabilized technique. A two-stage amplifier that consists of composite transistors and a recycling structure is proposed for the amplifier. Compared to a typical folded cascode CMOS amplifier, the proposed design has higher DC gain and slew rate as well as lower input-referred noise. This circuit has an adjustable second-order Gm-C LPF with very low power consumption. The amplifier achieves a midband gain of 70 dB and a -3dB bandwidth in the range 0.1-212 Hz. Moreover, the amplifier is designed in 0.18-µm CMOS process and the chip area of the proposed circuit with pads is 450×450 μm 2 . The adjustable LPF has a 100 Hz cut-off frequency. The proposed circuit has an input-referred noise of 0.7 μVrms, (0.1~100Hz) and a power consumption of 380 nW at 1 V supply.INDEX TERMS Fully recycling folded cascode amplifier, chopper-stabilized technique, EEG, Gm-C filter, low-noise design.

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