A 12GHz programmable fractional-n frequency divider with 0.18um CMOS technology

Heydarzadeh, Siavash; Torkzadeh, Pooya; Pourmina, Mohammad Ali

doi:10.1109/ceec.2013.6659440

Cited by 5 publications

(4 citation statements)

References 9 publications

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“…However, with the advancement of CMOS technology, the TSPC working frequency increased significantly. Extended TSPC (E-TSPC) designs were superior to the TSPC structure because E-TSPC flip-flops were utilized, which contained six transistors and were suitable for high frequency operation with low power consumption [8].…”

Section: Frequency Dividermentioning

confidence: 99%

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Mačaitis

Navickas

2019

Electronics

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This paper presents the design, simulation, and measurements of a low power, low phase noise 10.25–11.78 GHz LC digitally controlled oscillator (LC DCO) with extended true single phase clock (E-TSPC) frequency divider in 130 nm complementary metal–oxide–semiconductor (CMOS) technology for 5G intelligent transport systems. The main goal of this work was to design the LC DCO using a mature and low-cost 130 nm CMOS technology. The designed integrated circuit (IC) consisted of two parts: the LC DCO frequency generation and division circuit and an independent frequency divider testing circuit. The proposed LC DCO consisted of the following main blocks: the high Q-factor inductor, switched-capacitors block, cross-coupled transistors, and the current control block. Inductors with switched-capacitors block formed an LC tank. The designed E-TSPC frequency divider consisted of eight blocks connected in a series; each block increased the division ratio by a factor of two. The frequency of the input signal was divided in the region from two to 256 times using the designed divider. The main parameters of the designed E-TSPC divider and the LC DCO measurements were given as follows: LC DCO achieved a wide tuning range from 10.25 GHz to 11.78 GHz (1.53 GHz, 15.28% bandwidth); phase noise at 1 MHz offset frequency from LC DCO lowest carrier frequency was −113.42 dBc/Hz; phase noise at 1 MHz offset frequency from LC DCO highest carrier frequency was −110.51 dBc/Hz; The average power consumption of the designed LC DCO core and E-TSPC divider were 10.02 mW and 97.52 mW, respectively; the figure of merit (FOM) and the extended FOMT values of the proposed LC DCO were −183.52 dBc/Hz and −187.20 dBc/Hz, respectively. These FOM and FOMT results were achieved due to very low phase noise (−113.52 dBc/Hz) and a wide frequency tuning range (15.28%). The total layout area including the pads was 1.5 mm × 1.5 mm, with the largest part of the layout occupied by the proposed LC DCO (193 µm × 311 µm). The largest part of the LC DCO was occupied by the inductor 184 µm × 184 µm. The manufactured chip was packed into a quad flat no-leads (QFN) 20 pads package.

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Section: Frequency Dividermentioning

confidence: 99%

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Mačaitis

Navickas

2019

Electronics

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“…Tobulėjant KMOP integrinių grandynų technologijoms TSPC dažnio daliklių dažnis ženkliai padidėjo. Išplėstinis ETSPC dažnio daliklų tipas yra dar labiau pranašesnis nei TSPC, nes ETSPC dažnio dalikliuose, naudojama struktūra užtikrina dar didesnį veikimo dažnį bei mažesnę vartojamąją galią (Heydarzadeh, Torkzadeh, & Pourmina, 2013). Dažnio dalybos iš dviejų pakopos principinė elektrinė schema pateikta 3.19 a) paveiksle.…”

Section: Srovės Valdymo Blokasunclassified

Nanometrinių ir submikroninių integrinių grandynų įtampa ir skaitmeniniu būdu valdomiems generatoriams kūrimas ir tyrimas

Mačaitis¹

2019

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Disertacija rengta 2015-2019 metais Valstybiniame mokslinių tyrimų institute Fizinių ir technologijos mokslų centre. Vadovas prof. habil. dr. Romualdas NAVICKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001). Vilniaus Gedimino technikos universiteto elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo taryba: Pirmininkas prof. dr. Šarūnas PAULIKAS (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001). Nariai: dr. Alvydas LISAUSKAS (Lenkijos mokslų akademijos Aukšto slėgio fizikos institutas, fizika -N 002), dr. Vitalij NOVICKIJ (Vilniaus Gedimino technikos universitetas, elektros ir elektronikos inžinerija -T 001), dr. Česlovas ŠIMKEVIČIUS (Valstybinis mokslinių tyrimų institutas Fizinių ir technologijos mokslų centras, elektros ir elektronikos inžinerija -T 001), prof. dr. Algimantas VALINEVIČIUS (Kauno technologijos universitetas, elektros ir elektronikos inžinerija -T 001). Disertacija bus ginama viešame Elektros ir elektronikos inžinerijos mokslo krypties disertacijos gynimo tarybos posėdyje 2019 m. lapkričio 8 d. 13 val. Valstybinio mokslinių tyrimų instituto Fizinių ir technologijos mokslų centro posėdžių salėje D401.

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“…Then it converts the signal to rail-to-rail through two-stage inverters. Between the input and output of the first inverter there is a large resistance, it is used to make the DC point to be 0.9V by the negative feedback effect [6] of the large resistance.…”

Section: Circuit Designmentioning

confidence: 99%

A Programmable Frequency Divider for Multi-Standard Wireless Receivers

Wang¹,

Fan²,

Tang³

et al. 2014

AMM

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A programmable frequency divider based on divider-by-2/3 structure in fractional-N frequency synthesizer is presented, including a high speed divider-by-2 providing orthogonal signals for mixer. This paper firstly introduces two structures of programmable frequency divider, and analyzes the rationality of the circuit structure. Then it presents a method to determine the parameters of CMOS transistors in SCL structure. Finally, each component of the circuit is analyzed. The simulation results show that the programmable divider can work at 1 ~ 8 GHz and generates programmable division ratio from 32 to 127. This programmable frequency divider can be used in mobile communications, satellite navigation, short distance communication and other systems.

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A 12GHz programmable fractional-n frequency divider with 0.18um CMOS technology

Cited by 5 publications

References 9 publications

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Design of High Frequency, Low Phase Noise LC Digitally Controlled Oscillator for 5G Intelligent Transport Systems

Nanometrinių ir submikroninių integrinių grandynų įtampa ir skaitmeniniu būdu valdomiems generatoriams kūrimas ir tyrimas

A Programmable Frequency Divider for Multi-Standard Wireless Receivers

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