A Wide Tuning Range, 1GHz-2.5GHz DLL-Based Fractional Frequency Synthesizer

Torkzadeh, Pooya; Tajalli, Armin; Atarodi, M.

doi:10.1109/iscas.2005.1465764

Cited by 6 publications

(7 citation statements)

References 4 publications

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“…Whether on-or off-chip, cost and manufacturing issues prevent the use of huge banks of VCOs to cover SDR tuning ranges. Another way to get a broad tuning range is to have one or more VCOs and some combination of multipliers [28,29], dividers [30], or mixers [31]. Inevitably, the addition of these circuits comes at the cost of higher power consumption for equivalent noise and spurious performance.…”

Section: Phase-locked Loopsmentioning

confidence: 99%

Software‐Defined Transceivers

Cafaro

Stengel

2010

Multi‐Mode/Multi‐Band RF Transceivers for Wireless Communications

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Section: Phase-locked Loopsmentioning

confidence: 99%

Software‐Defined Transceivers

Cafaro

Stengel

2010

Multi‐Mode/Multi‐Band RF Transceivers for Wireless Communications

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“…Assuming an output voltage swing of V SW , the time constant of each channel will be: (18) in which, C L and R L are the total capacitive and resistive loads at the output nodes of delay stage, and I SS is the tail current of each delay cell. Since the capacitors of C L are roughly constant, the delay of each stage would be inversely proportional to the tail current of delay stage (I SS ) if V SW will be kept constant.…”

Section: Delay Linementioning

confidence: 99%

A Wide Tuning Range, Fractional Multiplying Delay-Locked Loop Topology for Frequency Hopping Applications

Tajalli

Torkzadeh

Atarodi³

2006

Analog Integr Circ Sig Process

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This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M + k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between two consecutive integer numbers. Operating in 2.5 GHz, total circuit including digital part consumes 15.5 mW from 1.8 V supply voltage. At the proposed architecture, reference clock is injected into a ring oscillator in specified times and to the specified delay-stages to synthesize the fractional frequency multiplication as well as resetting the accumulated jitter during previous cycles. Operating in maximum speed, simulated RMS (root-mean-square) and PTP (peak-to-peak) jitter values are 1.8 and 14.5 ps, respectively, while the settling time is 5 us.

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“…Therefore, it can only track frequency that is the integer multiple of the reference frequency. In [18], it mainly focuses on a DLL-based fractional frequency synthesizer. The phase detector (PD) compares a reference clock and generates an output frequency with fixed channel spacing (4/5/6.67 MHz).…”

Section: Introductionmentioning

confidence: 99%

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

Kuo

Hsu

2012

Circuit Theory & Apps

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SUMMARYA low-jitter and low-power dissipation delay-locked loop (DLL) is presented. A proposed multi-band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18 m CMOS process. The measured RMS and peak-to-peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz.

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A Wide Tuning Range, 1GHz-2.5GHz DLL-Based Fractional Frequency Synthesizer

Cited by 6 publications

References 4 publications

Software‐Defined Transceivers

Software‐Defined Transceivers

A Wide Tuning Range, Fractional Multiplying Delay-Locked Loop Topology for Frequency Hopping Applications

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

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