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An innovative vector-sum phase shifter with a full 360 variable phase-shift range in 0.18-m CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4 over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: 2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 0.75 mm . To the best of the authors' knowledge, this circuit is the first demonstration of microwave CMOS phase shifter with very low phase error over a wide bandwidth employing the vector sum method for all monolithic microwave integrated circuit phase shifters with 360 phase-control range to date.Index Terms-Active phase-shifter, CMOS analog integrated circuit, differential amplifier, I/Q network, phased array.

In this article, we present the room-temperature current-voltage characteristics of a nanometer scale (100×100nm2) metal-oxide-semiconductor capacitor containing few (less than 100) silicon nanoparticles. The layer of silicon nanoparticles is synthesized within the oxide of this capacitor by ultra low-energy ion implantation and annealing. Current fluctuations in the form of discrete current steps and sharp peaks appeared in the static and dynamic I(V) characteristics of the capacitor. These features have been associated to quantized charging and discharging of the nanoparticles and the resulting Coulomb interaction to the tunneling current.

This letter presents a novel method for network echo cancelation, based on a combination of normalized least mean square (NLMS) and proportionate NLMS (PNLMS) adaptive filtering algorithms. First, based on a rough analysis of PNLMS adaptation, it is indicated why after PNLMS initial fast convergence, it slows down. Then, the method used to overcome this deficiency is presented. Last, by showing some of the simulations, its improvement over PNLMS algorithm is shown.Index Terms-Adaptive filters, composite proportionate normalized least mean squares (PNLMS) and normalized least mean squares (NLMS) (CPNLMS), echo cancelation, proportionate normalized least mean squares (PNLMS).

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SUMMARYThis paper presents an RF Front-END for an 860-960 MHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-m technology. The chip area is 2.65 mm×1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires.