SUMMARYIn this paper, a pulse width modulation DC-DC converter with high step-up voltage gain is proposed. The proposed converter achieves high step-up voltage gain with appropriate duty ratio, coupled inductor, and voltage multiplier technique. The energy stored in the leakage inductor of the coupled inductor can be recycled in the proposed converter. Moreover, because both main and auxiliary switches can be turned on with zero-voltage switching, switching loss can be reduced by soft-switching technique. So the overall conversion efficiency is improved significantly. The theoretical steady-state analyses and the operating principles of the proposed converter are discussed in detail for both continuous conduction mode and discontinuous conduction mode. Finally, a laboratory prototype circuit of the proposed converter is implemented to verify the performance of the proposed converter.

Summary With the advancement of technology in renewable energy resources, the researchers and engineers have been more interested in utilizing such energy resources in various types of applications. To utilize commercial loads, the produced energy should be transferred to a high voltage (HV) DC link. In this paper, a double input HV gain DC‐DC converter is proposed. The soft switching capability and bidirectional power flow are achieved in the proposed topology using a coupled inductor structure. Thanks to an improved switching strategy for different power flow modes, soft switching operation of four main switches is achieved in low voltage (LV) to HV power flow direction. In HV to LV power transfer, the soft switching of the half of switches still exists. Moreover, a HV gain is achieved due to utilizing the coupled inductor. To validate the operation of proposed converter in different operation modes, a laboratory prototype was tested, which its results is presented in the paper.

SUMMARYThis paper presents an RF Front-END for an 860-960 MHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-m technology. The chip area is 2.65 mm×1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires.

An Interactive Artificial Bee Colony (IABC) Optimization based fuzzy (IABCF) to tune optimal gains of a Robust Proportional Integral Derivative (RPID) controller is proposed for the solution of multiarea automatic generation control (AGC) simulation problem in a restructured power system. One of the important problems in the proposed method is the exact tuning of the RPID parameters for achieving the desired level of robust performance. The problem of robustly tuning of RPID based AGC design is formulated as an optimization problem according to the time domain-based objective function, which is solved by the IABC technique that has a strong ability to find the most optimistic results. The robustness and effectiveness of the proffered method are shown on a two and four areas deregulated power system with possible contracted scenarios under large load demand and area disturbances in comparison with the other methods through FD and ITAE performance indices. The evaluation results show that the proposed control strategy achieves good robust performance for worldwide experience of automatic generation control in restructured systems parameters and load changes in the presence of system nonlinearities.

In this brief, a transformer-type power combiner for a fully integrated high-power CMOS power amplifier (PA) is presented. The proposed power combiner is composed of a number of transformers that, unlike the ones in conventional approaches, have different sizes. This leads to higher efficiency and smaller chip area. After considering several power stage topologies, analysis and optimization of the transformer network (the power combiner) are presented. To demonstrate the advantages of the proposed architecture, a 900-MHz CMOS PA with the proposed power combiner was implemented with a 0.18-µm radiofrequency CMOS process. The amplifier achieved an efficiency value of 24% at the maximum output power of 29.5 dBm.Index Terms-Efficiency optimization, power amplifier (PA), power combiner, transformer.

Increasing of renewable power plants has raised the need for intelligent energy management systems (EMSs). The aim of management system is to reduce energy absorbed from fossil sources. In this paper a layered behavioral based architecture named subsumption is employed for energy management in PV based power plant with storage devices and active load. In the proposed architecture components of the plant including SC, PV, battery, and the grid are organized in different layers. Each layer is implemented as a behavioral rule that can independently perceive and act in the environment. There is a hierarchy in the layers where lower layers have more priority and can inhibit higher layers. The layers use a simple protocol to communicate with management unit. Using this approach, a simple, fast, extensible, and fault tolerant EMS is achieved.

Power amplifiers (PAs) IntroductionRFID can provide automatic identification, tracking and management by radio frequency-based communication. RFID system is composed of two parts: transceivers and code reader. The main part of the RFID transmitter is linear power amplifier with high power. Since portable code readers are based on batteries, power amplifier consumes the largest part of power in code reader. So it is tried to have high efficiency. Moreover, linearity is one of the main parameters of power amplifiers (PAs). Class AB is widely used in wireless transceiver designs due to high linearity and high efficiency. In [1], a power amplifier composed of a parallel combination of amplifiers with Class A/AB led to improved linearity and increased power efficiency as well as reduced DC power consumption. In [2], the amplifier uses tuning technique in order to obtain the wide bandwidth and low power consumption, while it uses self-biased circuit to get high linearization. In [3], multi-band power amplifier uses a broadband matching network as a driver, while it uses reconfigurable matching network to increase the efficiency. In [4] and [5], the structure of CMOS power amplifier is constituted of input matching network, inter stage matching network, the output matching network, and a MOS switch-and varactor-based configurable tuning part .Uniformly coupled varactors with silicon on glass technology are used in order to implement tunable matching network, aiming at linearization improvement.In [6] and [7], the memory polynomial digital pre-distortion (DPD) technique is utilized for linearizing of amplifiers. Exploiting Class F, inverse Class F, Class J or Class AB/I are proposed for boosting of efficiency. In [8], [9] and [10] Doherty method and Envelope Elimination and Restoration (EER) techniques are presented for high efficiency. A combined approach that includes a switchable matching network using diplexer concepts and load line regulation as well as transistor reconfigurable area techniques are presented in [11]. In [12], a multi-L section, a quarter-wavelength transfer, and cone transmission line transfer are proposed for broadband matching networks. In [13], designing a linear amplifier with transistor level compensation technique is used to increase linearization of CMOS power amplifier.In this paper, first an overview of the proposed amplifier is presented and each block will be provided in detail. Then, the measured characteristics are shown at the 2400MHz frequency band.

Error Correction Code is very important in modern communication systems. BCH (Bose, Chaudhuri, and Hocqunghem) codes are being widely used in variety communication and storage systems. In this paper the construction and decoding BCH codes which are based on finite field arithmetic is introduced and also an improved algorithm for finding roots of polynomials over finite fields is proposed. This makes possible significant speed up of the decoding process of BCH codes.