A Highly Efficient and Linear Class AB Power Amplifier for RFID Application

Abstract

Power amplifiers (PAs) IntroductionRFID can provide automatic identification, tracking and management by radio frequency-based communication. RFID system is composed of two parts: transceivers and code reader. The main part of the RFID transmitter is linear power amplifier with high power. Since portable code readers are based on batteries, power amplifier consumes the largest part of power in code reader. So it is tried to have high efficiency. Moreover, linearity is one of the main parameters of power amplifiers (PAs). Class AB is widely used in wireless transceiver designs due to high linearity and high efficiency. In [1], a power amplifier composed of a parallel combination of amplifiers with Class A/AB led to improved linearity and increased power efficiency as well as reduced DC power consumption. In [2], the amplifier uses tuning technique in order to obtain the wide bandwidth and low power consumption, while it uses self-biased circuit to get high linearization. In [3], multi-band power amplifier uses a broadband matching network as a driver, while it uses reconfigurable matching network to increase the efficiency. In [4] and [5], the structure of CMOS power amplifier is constituted of input matching network, inter stage matching network, the output matching network, and a MOS switch-and varactor-based configurable tuning part .Uniformly coupled varactors with silicon on glass technology are used in order to implement tunable matching network, aiming at linearization improvement.In [6] and [7], the memory polynomial digital pre-distortion (DPD) technique is utilized for linearizing of amplifiers. Exploiting Class F, inverse Class F, Class J or Class AB/I are proposed for boosting of efficiency. In [8], [9] and [10] Doherty method and Envelope Elimination and Restoration (EER) techniques are presented for high efficiency. A combined approach that includes a switchable matching network using diplexer concepts and load line regulation as well as transistor reconfigurable area techniques are presented in [11]. In [12], a multi-L section, a quarter-wavelength transfer, and cone transmission line transfer are proposed for broadband matching networks. In [13], designing a linear amplifier with transistor level compensation technique is used to increase linearization of CMOS power amplifier.In this paper, first an overview of the proposed amplifier is presented and each block will be provided in detail. Then, the measured characteristics are shown at the 2400MHz frequency band.

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