SUMMARYIn this paper, a pulse width modulation DC-DC converter with high step-up voltage gain is proposed. The proposed converter achieves high step-up voltage gain with appropriate duty ratio, coupled inductor, and voltage multiplier technique. The energy stored in the leakage inductor of the coupled inductor can be recycled in the proposed converter. Moreover, because both main and auxiliary switches can be turned on with zero-voltage switching, switching loss can be reduced by soft-switching technique. So the overall conversion efficiency is improved significantly. The theoretical steady-state analyses and the operating principles of the proposed converter are discussed in detail for both continuous conduction mode and discontinuous conduction mode. Finally, a laboratory prototype circuit of the proposed converter is implemented to verify the performance of the proposed converter.
Summary With the advancement of technology in renewable energy resources, the researchers and engineers have been more interested in utilizing such energy resources in various types of applications. To utilize commercial loads, the produced energy should be transferred to a high voltage (HV) DC link. In this paper, a double input HV gain DC‐DC converter is proposed. The soft switching capability and bidirectional power flow are achieved in the proposed topology using a coupled inductor structure. Thanks to an improved switching strategy for different power flow modes, soft switching operation of four main switches is achieved in low voltage (LV) to HV power flow direction. In HV to LV power transfer, the soft switching of the half of switches still exists. Moreover, a HV gain is achieved due to utilizing the coupled inductor. To validate the operation of proposed converter in different operation modes, a laboratory prototype was tested, which its results is presented in the paper.
SUMMARYThis paper presents an RF Front-END for an 860-960 MHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-m technology. The chip area is 2.65 mm×1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power-added efficiency of 24% with a power gain of 20 dB, including the losses of the bond-wires.
An Interactive Artificial Bee Colony (IABC) Optimization based fuzzy (IABCF) to tune optimal gains of a Robust Proportional Integral Derivative (RPID) controller is proposed for the solution of multiarea automatic generation control (AGC) simulation problem in a restructured power system. One of the important problems in the proposed method is the exact tuning of the RPID parameters for achieving the desired level of robust performance. The problem of robustly tuning of RPID based AGC design is formulated as an optimization problem according to the time domain-based objective function, which is solved by the IABC technique that has a strong ability to find the most optimistic results. The robustness and effectiveness of the proffered method are shown on a two and four areas deregulated power system with possible contracted scenarios under large load demand and area disturbances in comparison with the other methods through FD and ITAE performance indices. The evaluation results show that the proposed control strategy achieves good robust performance for worldwide experience of automatic generation control in restructured systems parameters and load changes in the presence of system nonlinearities.
In this brief, a transformer-type power combiner for a fully integrated high-power CMOS power amplifier (PA) is presented. The proposed power combiner is composed of a number of transformers that, unlike the ones in conventional approaches, have different sizes. This leads to higher efficiency and smaller chip area. After considering several power stage topologies, analysis and optimization of the transformer network (the power combiner) are presented. To demonstrate the advantages of the proposed architecture, a 900-MHz CMOS PA with the proposed power combiner was implemented with a 0.18-µm radiofrequency CMOS process. The amplifier achieved an efficiency value of 24% at the maximum output power of 29.5 dBm.Index Terms-Efficiency optimization, power amplifier (PA), power combiner, transformer.
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