High Power Amplifier Based on a Transformer-Type Power Combiner in CMOS Technology

Javidan, Javad; Atarodi, M.; Luong, Howard C.

doi:10.1109/tcsii.2010.2082890

Cited by 17 publications

(9 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the number of turns in the secondary side increases, which lowers the self-resonance frequency and increases the area as compared to series combining technique. Javidan et al [19] achieved an implementation with a 40% smaller fingerprint as compared to Afsahi et al [18] and still attained good performance by using a transformer with different sizes.…”

Section: Class F Pamentioning

confidence: 99%

Energy efficiency in CMOS power amplifier designs for ultralow power mobile wireless communication systems

Mariappan¹,

Rajendran²,

Noh³

et al. 2020

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

Wireless communication standards keep evolving so that the requirement for high data rate operation can be fulfilled. This leads to the efforts in designing high linearity and low power consumption radio frequency power amplifier (RFPA) to support high data rate signal transmission and preserving battery life. The percentage of the DC power of the transceiver utilized by the power amplifier (PA) depends on the efficiency of the PA, user data rate, propagation conditions, signal modulations, and communication protocols. For example, the PA of a WLAN transceiver consumes 49% of the overall efficiency from the transmitter. Hence, operating the PA with minimum power consumption without trading-off the linearity is vital in order to achieve the goal of fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the efficiency in CMOS PA is discussed through the review of multifarious efficiency enhancement techniques in CMOS PA design. This is categorized into the review of efficiency in fundamental classes of PA in which Class E achieves the highest efficiency of 67%, followed by complex architectures utilized to enhance the efficiency level of the PA in which the outphasing architecture achieved the highest efficiency of 60.7%.

show abstract

Section: Class F Pamentioning

confidence: 99%

Energy efficiency in CMOS power amplifier designs for ultralow power mobile wireless communication systems

Mariappan¹,

Rajendran²,

Noh³

et al. 2020

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

show abstract

“…The series-combining DAT architecture [18] serves as both power combiner and matching network and can provide a solution with high efficiency but occupies a relatively large chip area. By using transformers with different sizes, Javidan et al [119] were able to shrink the area while still showing good performance. In examples of series power combination [120], [121], 1:1 transformers were used to combine the output of several amplifiers.…”

Section: Power Combination Using On-chip Transformersmentioning

confidence: 99%

A Review of Watt-Level CMOS RF Power Amplifiers

Johansson

Fritzin

2014

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

Abstract-This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage, and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched wattlevel PAs, as well as a few fully integrated CMOS PAs, is presented and discussed.

show abstract

“…Power combiners are one of the essential blocks in phased‐array receivers to combine the power of the phase‐shifted signals received by antenna elements. Many passive RF‐combiners have been proposed for millimeter‐wave such as transformer‐based power combiners, and Wilkinson‐based power combiners . The passive combiners utilizing transformers often exhibit poor power efficiency because of their low coupling factor and dramatically high conductor and substrate losses of on‐chip transformers at mm‐wave frequencies.…”

Section: Introductionmentioning

confidence: 99%

A 60 GHz semi‐distributed power combiner in 65 nm CMOS technology

Shamsadini

Mousavi

Moez

2018

Micro & Optical Tech Letters

View full text Add to dashboard Cite

In this paper, a novel architecture of power combiner based on a distributed amplifier topology is proposed for 60 GHz phased‐array antenna systems. A multi‐input single‐output power combiner is constructed by removing the input transmission lines of a distributed amplifier, the input signal delays are equalized by adding input delay/matching networks so that the amplified input signals are added constructively at the combiner's output. Fabricated in 65 nm CMOS process, measured results show a maximum insertion loss of 1 dB, and input/output reflections losses of better than 12 dB over the entire band of 57 GHz to 64 GHz while consuming 67 mW (56 mA) from a 1.2V DC supply.

show abstract

High Power Amplifier Based on a Transformer-Type Power Combiner in CMOS Technology

Cited by 17 publications

References 14 publications

Energy efficiency in CMOS power amplifier designs for ultralow power mobile wireless communication systems

Energy efficiency in CMOS power amplifier designs for ultralow power mobile wireless communication systems

A Review of Watt-Level CMOS RF Power Amplifiers

A 60 GHz semi‐distributed power combiner in 65 nm CMOS technology

Contact Info

Product

Resources

About