Energy efficiency in CMOS power amplifier designs for ultralow power mobile wireless communication systems

Abstract

Wireless communication standards keep evolving so that the requirement for high data rate operation can be fulfilled. This leads to the efforts in designing high linearity and low power consumption radio frequency power amplifier (RFPA) to support high data rate signal transmission and preserving battery life. The percentage of the DC power of the transceiver utilized by the power amplifier (PA) depends on the efficiency of the PA, user data rate, propagation conditions, signal modulations, and communication protocols. For example, the PA of a WLAN transceiver consumes 49% of the overall efficiency from the transmitter. Hence, operating the PA with minimum power consumption without trading-off the linearity is vital in order to achieve the goal of fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the efficiency in CMOS PA is discussed through the review of multifarious efficiency enhancement techniques in CMOS PA design. This is categorized into the review of efficiency in fundamental classes of PA in which Class E achieves the highest efficiency of 67%, followed by complex architectures utilized to enhance the efficiency level of the PA in which the outphasing architecture achieved the highest efficiency of 60.7%.

A State-of-the-Art Review on CMOS Radio Frequency Power Amplifiers for Wireless Communication Systems

“…When the auxiliary amplifier is inactive, the main amplifier faces a load resistance of RL. Whereas, if the auxiliary amplifier is active and generates a current, Iaux, the main amplifier, sees a load impedance as From (14), it is evident that the load impedance of the main amplifier can be varied by controlling the source current of the auxiliary amplifier (I aux ). This feature of the DPA is utilized to enhance its back-off efficiency, as illustrated in Figure 11 by controlling the source current of the auxiliary amplifier (Iaux).…”

“…Despite their disadvantages, CMOS-based PAs offer a promising alternative due to their cost-effectiveness and potential for integration with other circuits. Several techniques were developed to improve the efficiency, linearity, and bandwidth performance of CMOS PAs [14][15][16][17]. Efficiency enhancement techniques are usually employed for highly linear PAs that consume more DC power.…”