Abstract-This paper reviews the design of watt-level integrated CMOS RF power amplifiers (PAs) and state-of-the-art results in the literature. To reach watt-level output power from a single-chip CMOS PA, two main strategies can be identified: use of high supply voltage, and use of matching and power combination. High supply voltage limits are closely related to device design in the fabrication process. However, the maximum operating voltage can be improved by amplifier class selection, circuit solutions, and process modifications or mask changes. High output power can also be reached by the use of on-chip matching and power combination, commonly using on-chip transformers. Reliability often sets the limits for the PA design, and PA degradation mechanisms are reviewed. A compilation of state-of-the-art published results for linear and switched wattlevel PAs, as well as a few fully integrated CMOS PAs, is presented and discussed.
Abstract-This paper presents a behavioral model structure and a model-based phase-only predistortion method suitable for outphasing RF amplifiers. The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. The method has been used for EDGE and WCDMA signals applied to a Class-D outphasing RF amplifier with an on-chip transformer used for power combining in 90nm CMOS. The measured peak power at 2 GHz was +10.3 dBm with a drain efficiency and power-added efficiency of 39 % and 33 %, respectively. For an EDGE 8-PSK signal with a phase error of 3• between the two input outphasing signals, the measured power at 400 kHz offset was -65.9 dB with predistortion, compared to -53.5 dB without predistortion. For a WCDMA signal with the same phase error between the input signals, the measured ACLR at 5 MHz offset was -50.2 dBc with predistortion, compared to -38.0 dBc without predistortion.
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