A 60 GHz semi‐distributed power combiner in 65 nm CMOS technology

Abstract

In this paper, a novel architecture of power combiner based on a distributed amplifier topology is proposed for 60 GHz phased‐array antenna systems. A multi‐input single‐output power combiner is constructed by removing the input transmission lines of a distributed amplifier, the input signal delays are equalized by adding input delay/matching networks so that the amplified input signals are added constructively at the combiner's output. Fabricated in 65 nm CMOS process, measured results show a maximum insertion loss of 1 dB, and input/output reflections losses of better than 12 dB over the entire band of 57 GHz to 64 GHz while consuming 67 mW (56 mA) from a 1.2V DC supply.