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The emerging need for large amounts of flexible computational power on embedded devices motivated many researchers to incorporate reconfigurable logic together with an instruction-set-processor (ISP) into their architectures. This implies that tomorrow's applications will make use of both the ISP and the reconfigurable logic in order to provide the user with maximum performance. Today, however, a few stumbling blocks prevent these kind of heterogeneous architectures from becoming mainstream. The technology still lacks a form of run-time management infrastructure. This infrastructure should ease application development by shielding the programmer from the complexity of the system and by providing a clear application development API. This paper presents a novel approach for designing an operating system for reconfigurable systems (OS4RS). Creating such an operating system is an integral part of our ongoing research regarding reconfigurable computing. An initial version of our operating system was used to manage a reconfigurable systems demonstrator.0-7695-1926-1/03/$17.00 (C) 2003 IEEE

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DSP architectures often feature multiple register files with sparse connections to a large set of ALUs. For such DSPs, traditional register allocation algorithms suffer from a lot of problems, including a lack of retargetability and phase-ordering problems. This paper studies alternative register allocation techniques based on placement and routing. Different register file models are studied and evaluated on a state-of-the art coarse-grained reconfigurable array DSP, together with a new post-pass register allocator for rotating register files

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Abstract.Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving from a software-only view on the architecture to a real hardware implementation, as well as on the verification process of all involved tools.

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