No abstract

No abstract

No abstract

No abstract

In this paper we propose a C-b+ based cosimulation and cod&en environment. that allows to soecifv the timing behavior of the compo&ts of a complk h&dware-soft&m system independently of the functional refinement. While the hardware models are at a high functional abstraction level, thus resulting in a high simulation speed, yet the timing behavior can be specified with sufficient ~anultity to give relevant feedback concerning the timing of the software taski. We demonstrate this method on the design of the digital part of an ADSL modem.

This paper addresses the run time task scheduling problem on a multiprocessor platform for embedded systems, where energy consumption is a major concern, as opposed to the traditional static and dynamic scheduling approaches. Our approach i n tends to combine the advantages of the low run time complexity o f the static scheduler and the exibility of the dynamic scheduler and to optimize the system energy consumption at run time based on precomputed costperformance Pareto curves. We have applied our method to an ADSL modem application and the result shows the e ectiveness of our method.

WITH THE RAPID EVOLUTION of submicronprocess technology, manufacturers are integrating increasing numbers of components on one chip. A heterogeneous system on a chip (SOC) such as that shown in Figure 1 might include one or more programmable components-generalpurpose processor cores, digital signal processor cores, or application-specific intellectual property cores-as well as an analog front end, on-chip memory, I/O devices, and other application-specific ICs. Unfortunately, design technologies have fallen behind advances in processing technology, especially in the context of complex (possibly data-dominated) and very dynamic (partly nondeterministic) applications. SOC designers need a consistent system design technology that can cope with such characteristics and with evershortening time-to-market requirements. This technology should efficiently map these dynamic applications to the target realization while meeting all real-time and other constraints.Contemporary software (and hardware) design practices for this target class can be described only as ad hoc. The design trajecto-

No abstract