Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation

Bartic, T. Andrei; Desmet, D.; Mignolet, J.-Y.; Marescaux, Théodore; Verkest, D.; Vernalde, Serge; Lauwereins, Rudy; Miller, Joel B.; Robert, Frédéric

doi:10.1007/978-3-540-30117-2_65

Cited by 8 publications

(13 citation statements)

References 3 publications

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“…Much work focus on generating, exploring, evaluating, formalising, and comparing NoC architectures and instantiations [2,5,8,14,22,25,38,39,45,48,52,63]. However, only a few works address guaranteed services [25,39,45], and most works are limited to evaluations of a single small-scale example, or only a few steps of the design flow, as exemplified by the overview in [48].…”

Section: Functional Scalabilitymentioning

confidence: 99%

“…A few NoC design flows have been demonstrated on FPGA [2,22,33,43,52], predominantly using simple media-centric applications like M-JPEG [33] and MPEG-2 [43]. In addition to FPGAs, complete NoC-based SoC ASICs are presented in [7,17,72] together with a post-layout evaluation.…”

Section: Functional Scalabilitymentioning

confidence: 99%

“…However, neither of the works evaluate the scalability and instead focus on a single design point. Moreover, rather than considering the IPs given, the works in [2,22,43,52,72] customise the entire system to fit with the NoC, e.g. by modifying the IPs [43] or adding NoC-specific instructions [72].…”

Section: Functional Scalabilitymentioning

confidence: 99%

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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

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A growing number of applications are integrated on the same System on Chip in the form of hardware and software Intellectual Property (IP). Many applications have firm or soft real-time requirements and require bounds on latency and throughput. To accommodate the growing number of application requirements, the on-chip interconnect must offer scalability on the physical, architectural and functional level.Networks on Chip (NoC) are proposed as a scalable communication architecture that is also able to deliver guaranteed performance. Traditionally, NoCs focus on delivering physical and architectural scalability. The functional scalability, i.e. the ability to satisfy an increasing number of increasingly demanding requirements with a constant cost/performance ratio, is often overlooked. The onus is on the interconnect design flow that translates user requirements to an interconnect instance. While mature tooling exists for many of the IPs, interconnect design flows are an active research area, with few concrete examples, and few large-scale case studies.As the main contribution of this work, we demonstrate a complete operational interconnect design flow for multiple real-time applications, and quantitatively evaluate the functional scalability on two large-scale industrial case studies. We illustrate the steps of the flow, going from requirement specification all the way to simulation of synthesised netlists in a 90 nm and 65 nm low-power standard-cell technology. We show that the interconnect and design flow offer scalability, on the physical, architectural as well as the functional level.

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Section: Functional Scalabilitymentioning

confidence: 99%

Section: Functional Scalabilitymentioning

confidence: 99%

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A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications

Hansson

Goossens

2011

Des Autom Embed Syst

View full text Add to dashboard Cite

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“…This allows one to explore, evaluate, and compare a wide range of NoC solutions. Two models for designing and implementing NoC are proposed in [5], one written in VHDL for synthesis, and another in SystemC for cycle-accurate simulation. HERMES has also been implemented on the FPGA and uses R8 processors to validate the interconnection network [17].…”

Section: Related Workmentioning

confidence: 99%

“…Some work that focuses on generating processing nodes automatically is presented in [8,12,19]. Automation of network fabric generation is presented in [5][6][7]14]. However, to the best of our knowledge, there is no fully integrated tool-flow for generating network-based MPSoC.…”

Section: Introductionmentioning

confidence: 99%