An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip

Kumar, Akash; Hansson, Andreas; Huisken, Jos; Corporaal, Henk

doi:10.1109/date.2007.364577

Cited by 55 publications

(35 citation statements)

References 17 publications

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“…Yet another flow for generating MPSoCs for FPGAs has been presented in Kumar et al [2007b]. However, that flow focuses on generic MPSoCs and not on application-specific architectures.…”

Section: Related Workmentioning

confidence: 99%

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

Kumar

Fernando

et al. 2008

ACM Trans. Des. Autom. Electron. Syst.

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Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semiautomated, time consuming, and error prone.In this article, we present a design methodology to generate multiprocessor systems in a systematic and fully automated way for multiple use-cases. Techniques are presented to merge multiple use-cases into one hardware design to minimize cost and design time, making it well suited for fast design-space exploration (DSE) in MPSoC systems. Heuristics to partition use-cases are also presented such that each partition can fit in an FPGA, and all use-cases can be catered for.The proposed methodology is implemented into a tool for Xilinx FPGAs for evaluation. The tool is also made available online for the benefit of the research community and is used to carry out a DSE case study with multiple use-cases of real-life applications: H263 and JPEG decoders. The generation of the entire design takes about 100 ms, and the whole DSE was completed in 45 minutes, including FPGA mapping and synthesis. The heuristics used for use-case Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or direct commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212) 869-0481, or permissions@acm.org. partitioning reduce the design-exploration time elevenfold in a case study with mobile-phone applications.

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“…Yet another flow for generating MPSoCs for FPGAs has been presented in Kumar et al [2007b]. However, that flow focuses on generic MPSoCs and not on application-specific architectures.…”

Section: Related Workmentioning

confidence: 99%

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

Kumar

Fernando

et al. 2008

ACM Trans. Des. Autom. Electron. Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Yet another flow for generating MPSoC for FPGA has been presented in [11]. However, this flow focuses on generic MPSoC and not on application-specific architectures.…”

Section: Related Workmentioning

confidence: 99%

“…However, this flow focuses on generic MPSoC and not on application-specific architectures. Further, the work in [11] uses networks-on-chip for communication fabric, while in our approach dedicated links are Xilinx provides a tool-chain as well to generate designs with multiple processors and peripherals [8]. However, most of the features are limited to designs with only a bus-based processor-coprocessor pair with shared-memory.…”

Section: Related Workmentioning

confidence: 99%

Multi-Processor System-Level Synthesis for Multiple Applications on Platform FPGA

Kumar

Fernando

et al. 2007

2007 International Conference on Field Programmable Logic and Applications

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Multiprocessor systems-on-chip (MPSoC) are being developed in increasing numbers to support the high number of applications running on modern embedded systems. Designing and programming such systems prove to be a major challenge. Most of the current design methodologies rely on creating the design by hand, and are therefore error-prone and time-consuming. This also limits the number of design points that can be explored. While some efforts have been made to automate the flow and raise the abstraction level, these are still limited to single-application designs.In this paper, we present a design methodology to generate and program MPSoC designs in a systematic and automated way for multiple applications. The architecture is automatically inferred from the application specifications, and customized for it. The flow is ideal for fast design space exploration (DSE) in MPSoC systems. We present results of a case study to compute the buffer-throughput trade-offs in real-life applications, H263 and JPEG decoders. The generation of the entire project takes about 100ms, and the whole DSE was completed in 45 minutes, including the FPGA mapping and synthesis.

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“…This NoC can be dynamically configured with respect to routing, switching and data packet size, but all the required resources have to be allocated at design time, since at run-time it is only possible to dynamically change a limited number of parameters. A similar approach can be found in [10], where the proposed NoC can be configured at run-time, but only with respect to memories content, resources addressing and control parameters, while topology, buffers size and port connections have to be determined at design time.…”

Section: State Of the Artmentioning

confidence: 99%

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Rana

Atienza

Santambrogio

et al. 2010

IFIP Advances in Information and Communication Technology

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Summary. Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications. In this context, methods that can lead to versatility enhancements of initial NoC designs to changing working conditions, imposed by variable sets of executed real-life applications at each moment in time, are very important for designing competitive NoCs in industrial SoCs.In this work, we present a run-time reconfigurable NoC framework based on the partial dynamic reconfiguration capabilities of Field-Programmable Gate Arrays (FPGAs). This new NoC framework can dynamically create/delete express lines between SoC components (implementing dynamically circuit-switching channels) and perform run-time NoC topology and routing-table reconfigurations to handle interconnection congestion, with a very limited performance overhead. Moreover, we show in our experimental results that the addition of these dynamic reconfiguration capabilities into basic NoCs using our framework only implies a very limited area overhead (around 10% on average) with respect to the initial NoC designs; thus, it can bring great benefits when compared to traditional non-reconfigurable NoC design approaches for worst-case bandwidth requirements in SoCs with many possible sets of running applications.

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An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip

Abstract: Multi-Processor System on Chip (MPSoC)

Cited by 55 publications

References 17 publications

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA

Multi-Processor System-Level Synthesis for Multiple Applications on Platform FPGA

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

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