A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Abstract

Summary. Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications. In this context, methods that can lead to versatility enhancements of initial NoC designs to changing working conditions, imposed by variable sets of executed real-life applications at each moment in time, are very important for designing competitive NoCs in industrial SoCs.In this work, we present a run-time reconfigurable NoC framework based on the partial dynamic reconfiguration capabilities of Field-Programmable Gate Arrays (FPGAs). This new NoC framework can dynamically create/delete express lines between SoC components (implementing dynamically circuit-switching channels) and perform run-time NoC topology and routing-table reconfigurations to handle interconnection congestion, with a very limited performance overhead. Moreover, we show in our experimental results that the addition of these dynamic reconfiguration capabilities into basic NoCs using our framework only implies a very limited area overhead (around 10% on average) with respect to the initial NoC designs; thus, it can bring great benefits when compared to traditional non-reconfigurable NoC design approaches for worst-case bandwidth requirements in SoCs with many possible sets of running applications.

A Survey on Reconfigurable System-on-Chips

“…Finally, the NoC proposals need to be implemented at RTL (Register Transfer Level) by describing the design in VHDL or Verilog HDL and prototyped on a FPGA platform (e.g. [47,58,59]). 6 State of the Art on Reconfigurable SoCs…”

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design

“…The hardware architecture we employ in this paper is logically divided into two layers: the communication layer, and the computation layer, as proposed in [21]. The computation layer includes the cores of the executed application, while the communication layer guarantees connectivity between them.…”

On-Chip Interconnect mechanism based on CDMA

“…As more and more components are integrated into an on-chip system, communication issues become complicated. [1] Network-on-chip (NoC) is proposed to solve the OnChip communication problems.…”

“…In order to eliminate variance of data transfer latency and complexity incurred by routing issues in a P2P connected NoC, [1] an On-Chip network which applies a code division multiple access (CDMA) technique is introduced in this paper. As one of the spread-spectrum techniques, CDMA technique has been widely used in wireless communication systems because it has great bandwidth efficiency and multiple access capability .CDMA technique applies a set of orthogonal codes to encode the data from different users before transmission in shared communication media.…”