A Survey on Reconfigurable System-on-Chips

Abstract

Abstract-The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation of multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is the integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

Design-Space Exploration of Application-specific Instruction-set Processor Design

“…A lot of different architectures were proposed for the CGRAs in the last decades [6]. Based on the reconfiguration phase of CGRAs, they can be categorized into three different groups.…”

“…Based on the reconfiguration phase of CGRAs, they can be categorized into three different groups. In the first group CGRAs, the CGRA has been configured at the beginning, and then the CGRA goes to the execution phase, such as PACT XPP III [6]. The second group of CGRAs refers to those that have been reconfigured along with the execution phase.…”

“…Many different architectures were proposed to improve the performance of the process-intensive part of the application, such as custom instructions extraction [5], using field-programmable gate arrays (FPGAs) or coarsegrained reconfigurable arrays (CGRAs) as a coprocessor [1] or using a graphics processing unit (GPU) to parallelize the loops [1]. CGRAs established their power in both highperformance and low-power domains [1,6].…”

Aceleradores Reconfiguráveis no Projeto Multicore: uma análise de custo versus benefício

“…A combinação de processadores de propósito geral com arquiteturas reconfiguráveis como aceleradores tem sido vastamente utilizada (Kuon et al, 2008;Tehre & Kshirsagar, 2012;Kareemullah, Janakiraman & Kumar, 2017;Nguyen, Le-Van & Tran, 2018). Nessa combinação, os processadores de propósito geral são responsáveis por controlar a lógica reconfigurável e executar o código do programa que não pode ser eficientemente acelerado (Compton & Hauck, 2002).…”

A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI

“…Furthermore, including an FPGA in a Multi-Processor System on Chip (MPSoC) ensures a level of flexibility and adaptivity unreachable with a custom Application Specific Integrated Circuit (ASIC): surrounding the CPUs with programmable logic supports the modification of the CPS functionalities during its lifetime according to each specific situation. For these reasons and taking into account the analysis of Reconfigurable System on Chip in [6] (2018), it is clear that, as shown in Fig 1, "Hybrid Reconfigurable SoCs" (hereafter called Heterogeneous MPSoCs) have a fair trade-off between performance and power consumption in one side versus flexibility in the other side. Hence, they will play a central role in the evolution of the CPS.…”